--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __INC_HAL8812PHYREG_H__\r
+#define __INC_HAL8812PHYREG_H__\r
+/*--------------------------Define Parameters-------------------------------*/\r
+//\r
+// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\r
+// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\r
+// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\r
+// 3. RF register 0x00-2E\r
+// 4. Bit Mask for BB/RF register\r
+// 5. Other defintion for BB/RF R/W\r
+//\r
+\r
+\r
+// BB Register Definition\r
+\r
+#define rCCAonSec_Jaguar 0x838\r
+#define rPwed_TH_Jaguar 0x830\r
+\r
+// BW and sideband setting\r
+#define rBWIndication_Jaguar 0x834\r
+#define rL1PeakTH_Jaguar 0x848\r
+#define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/\r
+#define rRFMOD_Jaguar 0x8ac //RF mode \r
+#define rADC_Buf_Clk_Jaguar 0x8c4\r
+#define rRFECTRL_Jaguar 0x900\r
+#define bRFMOD_Jaguar 0xc3\r
+#define rCCK_System_Jaguar 0xa00 // for cck sideband\r
+#define bCCK_System_Jaguar 0x10\r
+\r
+// Block & Path enable\r
+#define rOFDMCCKEN_Jaguar 0x808 // OFDM/CCK block enable\r
+#define bOFDMEN_Jaguar 0x20000000\r
+#define bCCKEN_Jaguar 0x10000000\r
+#define rRxPath_Jaguar 0x808 // Rx antenna\r
+#define bRxPath_Jaguar 0xff\r
+#define rTxPath_Jaguar 0x80c // Tx antenna\r
+#define bTxPath_Jaguar 0x0fffffff\r
+#define rCCK_RX_Jaguar 0xa04 // for cck rx path selection\r
+#define bCCK_RX_Jaguar 0x0c000000 \r
+#define rVhtlen_Use_Lsig_Jaguar 0x8c3 // Use LSIG for VHT length\r
+\r
+// RF read/write-related\r
+#define rHSSIRead_Jaguar 0x8b0 // RF read addr\r
+#define bHSSIRead_addr_Jaguar 0xff\r
+#define bHSSIRead_trigger_Jaguar 0x100\r
+#define rA_PIRead_Jaguar 0xd04 // RF readback with PI\r
+#define rB_PIRead_Jaguar 0xd44 // RF readback with PI\r
+#define rA_SIRead_Jaguar 0xd08 // RF readback with SI\r
+#define rB_SIRead_Jaguar 0xd48 // RF readback with SI\r
+#define rRead_data_Jaguar 0xfffff\r
+#define rA_LSSIWrite_Jaguar 0xc90 // RF write addr\r
+#define rB_LSSIWrite_Jaguar 0xe90 // RF write addr\r
+#define bLSSIWrite_data_Jaguar 0x000fffff\r
+#define bLSSIWrite_addr_Jaguar 0x0ff00000\r
+\r
+\r
+\r
+// YN: mask the following register definition temporarily \r
+#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch\r
+#define rFPGA0_XB_RFInterfaceOE 0x864\r
+\r
+#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control\r
+#define rFPGA0_XCD_RFInterfaceSW 0x874\r
+\r
+//#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter\r
+//#define rFPGA0_XCD_RFParameter 0x87c\r
+\r
+//#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??\r
+//#define rFPGA0_AnalogParameter2 0x884\r
+//#define rFPGA0_AnalogParameter3 0x888\r
+//#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy\r
+//#define rFPGA0_AnalogParameter4 0x88c\r
+\r
+\r
+// CCK TX scaling\r
+#define rCCK_TxFilter1_Jaguar 0xa20\r
+#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000\r
+#define bCCK_TxFilter1_C1_Jaguar 0xff000000\r
+#define rCCK_TxFilter2_Jaguar 0xa24\r
+#define bCCK_TxFilter2_C2_Jaguar 0x000000ff\r
+#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00\r
+#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000\r
+#define bCCK_TxFilter2_C5_Jaguar 0xff000000\r
+#define rCCK_TxFilter3_Jaguar 0xa28\r
+#define bCCK_TxFilter3_C6_Jaguar 0x000000ff\r
+#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00\r
+\r
+\r
+// YN: mask the following register definition temporarily\r
+//#define rPdp_AntA 0xb00 \r
+//#define rPdp_AntA_4 0xb04\r
+//#define rConfig_Pmpd_AntA 0xb28\r
+//#define rConfig_AntA 0xb68\r
+//#define rConfig_AntB 0xb6c\r
+//#define rPdp_AntB 0xb70\r
+//#define rPdp_AntB_4 0xb74\r
+//#define rConfig_Pmpd_AntB 0xb98\r
+//#define rAPK 0xbd8\r
+\r
+// RXIQC\r
+#define rA_RxIQC_AB_Jaguar 0xc10 //RxIQ imblance matrix coeff. A & B\r
+#define rA_RxIQC_CD_Jaguar 0xc14 //RxIQ imblance matrix coeff. C & D\r
+#define rA_TxScale_Jaguar 0xc1c // Pah_A TX scaling factor\r
+#define rB_TxScale_Jaguar 0xe1c // Path_B TX scaling factor\r
+#define rB_RxIQC_AB_Jaguar 0xe10 //RxIQ imblance matrix coeff. A & B\r
+#define rB_RxIQC_CD_Jaguar 0xe14 //RxIQ imblance matrix coeff. C & D\r
+#define b_RxIQC_AC_Jaguar 0x02ff // bit mask for IQC matrix element A & C\r
+#define b_RxIQC_BD_Jaguar 0x02ff0000 // bit mask for IQC matrix element A & C\r
+\r
+\r
+// DIG-related\r
+#define rA_IGI_Jaguar 0xc50 // Initial Gain for path-A\r
+#define rB_IGI_Jaguar 0xe50 // Initial Gain for path-B\r
+#define rOFDM_FalseAlarm1_Jaguar 0xf48 // counter for break\r
+#define rOFDM_FalseAlarm2_Jaguar 0xf4c // counter for spoofing\r
+#define rCCK_FalseAlarm_Jaguar 0xa5c // counter for cck false alarm\r
+#define b_FalseAlarm_Jaguar 0xffff\r
+#define rCCK_CCA_Jaguar 0xa08 // cca threshold\r
+#define bCCK_CCA_Jaguar 0x00ff0000\r
+\r
+// Tx Power Ttraining-related\r
+#define rA_TxPwrTraing_Jaguar 0xc54\r
+#define rB_TxPwrTraing_Jaguar 0xe54\r
+\r
+// Report-related\r
+#define rOFDM_ShortCFOAB_Jaguar 0xf60 \r
+#define rOFDM_LongCFOAB_Jaguar 0xf64\r
+#define rOFDM_EndCFOAB_Jaguar 0xf70\r
+#define rOFDM_AGCReport_Jaguar 0xf84\r
+#define rOFDM_RxSNR_Jaguar 0xf88\r
+#define rOFDM_RxEVMCSI_Jaguar 0xf8c\r
+#define rOFDM_SIGReport_Jaguar 0xf90\r
+\r
+// Misc functions\r
+#define rEDCCA_Jaguar 0x8a4 // EDCCA\r
+#define bEDCCA_Jaguar 0xffff\r
+#define rAGC_table_Jaguar 0x82c // AGC tabel select\r
+#define bAGC_table_Jaguar 0x3\r
+#define b_sel5g_Jaguar 0x1000 // sel5g\r
+#define b_LNA_sw_Jaguar 0x8000 // HW/WS control for LNA\r
+#define rFc_area_Jaguar 0x860 // fc_area \r
+#define bFc_area_Jaguar 0x1ffe000\r
+#define rSingleTone_ContTx_Jaguar 0x914\r
+\r
+// RFE\r
+#define rA_RFE_Pinmux_Jaguar 0xcb0 // Path_A RFE cotrol pinmux\r
+#define rB_RFE_Pinmux_Jaguar 0xeb0 // Path_B RFE control pinmux\r
+#define rA_RFE_Inv_Jaguar 0xcb4 // Path_A RFE cotrol \r
+#define rB_RFE_Inv_Jaguar 0xeb4 // Path_B RFE control\r
+#define rA_RFE_Jaguar 0xcb8 // Path_A RFE cotrol \r
+#define rB_RFE_Jaguar 0xeb8 // Path_B RFE control\r
+#define r_ANTSEL_SW_Jaguar 0x900 // ANTSEL SW Control\r
+#define bMask_RFEInv_Jaguar 0x3ff00000\r
+#define bMask_AntselPathFollow_Jaguar 0x00030000\r
+\r
+// TX AGC \r
+#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20\r
+#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24\r
+#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28\r
+#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c\r
+#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30\r
+#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34\r
+#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38\r
+#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c\r
+#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40\r
+#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44\r
+#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48\r
+#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c\r
+#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20\r
+#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24\r
+#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28\r
+#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c\r
+#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30\r
+#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34\r
+#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38\r
+#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c\r
+#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40\r
+#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44\r
+#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48\r
+#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c\r
+#define bTxAGC_byte0_Jaguar 0xff\r
+#define bTxAGC_byte1_Jaguar 0xff00\r
+#define bTxAGC_byte2_Jaguar 0xff0000\r
+#define bTxAGC_byte3_Jaguar 0xff000000\r
+\r
+// IQK YN: temporaily mask this part\r
+//#define rFPGA0_IQK 0xe28\r
+//#define rTx_IQK_Tone_A 0xe30\r
+//#define rRx_IQK_Tone_A 0xe34\r
+//#define rTx_IQK_PI_A 0xe38\r
+//#define rRx_IQK_PI_A 0xe3c\r
+\r
+//#define rTx_IQK 0xe40\r
+//#define rRx_IQK 0xe44\r
+//#define rIQK_AGC_Pts 0xe48\r
+//#define rIQK_AGC_Rsp 0xe4c\r
+//#define rTx_IQK_Tone_B 0xe50\r
+//#define rRx_IQK_Tone_B 0xe54\r
+//#define rTx_IQK_PI_B 0xe58\r
+//#define rRx_IQK_PI_B 0xe5c\r
+//#define rIQK_AGC_Cont 0xe60\r
+\r
+\r
+// AFE-related\r
+#define rA_AFEPwr1_Jaguar 0xc60 // dynamic AFE power control\r
+#define rA_AFEPwr2_Jaguar 0xc64 // dynamic AFE power control\r
+#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68\r
+#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c\r
+#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70\r
+#define rA_Tx2Tx_RXCCK_Jaguar 0xc74\r
+#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78\r
+#define rA_Rx2Rx_BT_Jaguar 0xc7c\r
+#define rA_sleep_nav_Jaguar 0xc80\r
+#define rA_pmpd_Jaguar 0xc84\r
+#define rB_AFEPwr1_Jaguar 0xe60 // dynamic AFE power control\r
+#define rB_AFEPwr2_Jaguar 0xe64 // dynamic AFE power control\r
+#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68\r
+#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c\r
+#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70\r
+#define rB_Tx2Tx_RXCCK_Jaguar 0xe74\r
+#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78\r
+#define rB_Rx2Rx_BT_Jaguar 0xe7c\r
+#define rB_sleep_nav_Jaguar 0xe80\r
+#define rB_pmpd_Jaguar 0xe84\r
+\r
+\r
+// YN: mask these registers temporaily\r
+//#define rTx_Power_Before_IQK_A 0xe94\r
+//#define rTx_Power_After_IQK_A 0xe9c\r
+\r
+//#define rRx_Power_Before_IQK_A 0xea0\r
+//#define rRx_Power_Before_IQK_A_2 0xea4\r
+//#define rRx_Power_After_IQK_A 0xea8\r
+//#define rRx_Power_After_IQK_A_2 0xeac\r
+\r
+//#define rTx_Power_Before_IQK_B 0xeb4\r
+//#define rTx_Power_After_IQK_B 0xebc\r
+\r
+//#define rRx_Power_Before_IQK_B 0xec0\r
+//#define rRx_Power_Before_IQK_B_2 0xec4\r
+//#define rRx_Power_After_IQK_B 0xec8\r
+//#define rRx_Power_After_IQK_B_2 0xecc\r
+\r
+\r
+// RSSI Dump\r
+#define rA_RSSIDump_Jaguar 0xBF0\r
+#define rB_RSSIDump_Jaguar 0xBF1\r
+#define rS1_RXevmDump_Jaguar 0xBF4 \r
+#define rS2_RXevmDump_Jaguar 0xBF5\r
+#define rA_RXsnrDump_Jaguar 0xBF6\r
+#define rB_RXsnrDump_Jaguar 0xBF7\r
+#define rA_CfoShortDump_Jaguar 0xBF8 \r
+#define rB_CfoShortDump_Jaguar 0xBFA\r
+#define rA_CfoLongDump_Jaguar 0xBEC\r
+#define rB_CfoLongDump_Jaguar 0xBEE\r
+ \r
+\r
+// RF Register\r
+//\r
+#define RF_AC_Jaguar 0x00 // \r
+#define RF_RF_Top_Jaguar 0x07 // \r
+#define RF_TXLOK_Jaguar 0x08 // \r
+#define RF_TXAPK_Jaguar 0x0B\r
+#define RF_CHNLBW_Jaguar 0x18 // RF channel and BW switch\r
+#define RF_RCK1_Jaguar 0x1c // \r
+#define RF_RCK2_Jaguar 0x1d\r
+#define RF_RCK3_Jaguar 0x1e\r
+#define RF_ModeTableAddr 0x30\r
+#define RF_ModeTableData0 0x31\r
+#define RF_ModeTableData1 0x32\r
+#define RF_TxLCTank_Jaguar 0x54\r
+#define RF_APK_Jaguar 0x63\r
+#define RF_LCK 0xB4\r
+#define RF_WeLut_Jaguar 0xEF\r
+\r
+#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300\r
+#define bRF_CHNLBW_BW 0xc00\r
+\r
+\r
+//\r
+// RL6052 Register definition\r
+//\r
+#define RF_AC 0x00 // \r
+#define RF_IPA_A 0x0C // \r
+#define RF_TXBIAS_A 0x0D\r
+#define RF_BS_PA_APSET_G9_G11 0x0E\r
+#define RF_MODE1 0x10 // \r
+#define RF_MODE2 0x11 // \r
+#define RF_CHNLBW 0x18 // RF channel and BW switch\r
+#define RF_RCK_OS 0x30 // RF TX PA control\r
+#define RF_TXPA_G1 0x31 // RF TX PA control\r
+#define RF_TXPA_G2 0x32 // RF TX PA control\r
+#define RF_TXPA_G3 0x33 // RF TX PA control\r
+#define RF_0x52 0x52\r
+#define RF_WE_LUT 0xEF\r
+\r
+#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))\r
+#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))\r
+\r
+//\r
+//Bit Mask\r
+//\r
+// 1. Page1(0x100)\r
+#define bBBResetB 0x100 // Useless now?\r
+#define bGlobalResetB 0x200\r
+#define bOFDMTxStart 0x4\r
+#define bCCKTxStart 0x8\r
+#define bCRC32Debug 0x100\r
+#define bPMACLoopback 0x10\r
+#define bTxLSIG 0xffffff\r
+#define bOFDMTxRate 0xf\r
+#define bOFDMTxReserved 0x10\r
+#define bOFDMTxLength 0x1ffe0\r
+#define bOFDMTxParity 0x20000\r
+#define bTxHTSIG1 0xffffff\r
+#define bTxHTMCSRate 0x7f\r
+#define bTxHTBW 0x80\r
+#define bTxHTLength 0xffff00\r
+#define bTxHTSIG2 0xffffff\r
+#define bTxHTSmoothing 0x1\r
+#define bTxHTSounding 0x2\r
+#define bTxHTReserved 0x4\r
+#define bTxHTAggreation 0x8\r
+#define bTxHTSTBC 0x30\r
+#define bTxHTAdvanceCoding 0x40\r
+#define bTxHTShortGI 0x80\r
+#define bTxHTNumberHT_LTF 0x300\r
+#define bTxHTCRC8 0x3fc00\r
+#define bCounterReset 0x10000\r
+#define bNumOfOFDMTx 0xffff\r
+#define bNumOfCCKTx 0xffff0000\r
+#define bTxIdleInterval 0xffff\r
+#define bOFDMService 0xffff0000\r
+#define bTxMACHeader 0xffffffff\r
+#define bTxDataInit 0xff\r
+#define bTxHTMode 0x100\r
+#define bTxDataType 0x30000\r
+#define bTxRandomSeed 0xffffffff\r
+#define bCCKTxPreamble 0x1\r
+#define bCCKTxSFD 0xffff0000\r
+#define bCCKTxSIG 0xff\r
+#define bCCKTxService 0xff00\r
+#define bCCKLengthExt 0x8000\r
+#define bCCKTxLength 0xffff0000\r
+#define bCCKTxCRC16 0xffff\r
+#define bCCKTxStatus 0x1\r
+#define bOFDMTxStatus 0x2\r
+\r
+\r
+//\r
+// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\r
+// 1. Page1(0x100)\r
+//\r
+#define rPMAC_Reset 0x100\r
+#define rPMAC_TxStart 0x104\r
+#define rPMAC_TxLegacySIG 0x108\r
+#define rPMAC_TxHTSIG1 0x10c\r
+#define rPMAC_TxHTSIG2 0x110\r
+#define rPMAC_PHYDebug 0x114\r
+#define rPMAC_TxPacketNum 0x118\r
+#define rPMAC_TxIdle 0x11c\r
+#define rPMAC_TxMACHeader0 0x120\r
+#define rPMAC_TxMACHeader1 0x124\r
+#define rPMAC_TxMACHeader2 0x128\r
+#define rPMAC_TxMACHeader3 0x12c\r
+#define rPMAC_TxMACHeader4 0x130\r
+#define rPMAC_TxMACHeader5 0x134\r
+#define rPMAC_TxDataType 0x138\r
+#define rPMAC_TxRandomSeed 0x13c\r
+#define rPMAC_CCKPLCPPreamble 0x140\r
+#define rPMAC_CCKPLCPHeader 0x144\r
+#define rPMAC_CCKCRC16 0x148\r
+#define rPMAC_OFDMRxCRC32OK 0x170\r
+#define rPMAC_OFDMRxCRC32Er 0x174\r
+#define rPMAC_OFDMRxParityEr 0x178\r
+#define rPMAC_OFDMRxCRC8Er 0x17c\r
+#define rPMAC_CCKCRxRC16Er 0x180\r
+#define rPMAC_CCKCRxRC32Er 0x184\r
+#define rPMAC_CCKCRxRC32OK 0x188\r
+#define rPMAC_TxStatus 0x18c\r
+\r
+//\r
+// 3. Page8(0x800)\r
+//\r
+#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??\r
+\r
+#define rFPGA0_TxInfo 0x804 // Status report??\r
+#define rFPGA0_PSDFunction 0x808\r
+#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?\r
+\r
+#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register\r
+#define rFPGA0_XA_HSSIParameter2 0x824\r
+#define rFPGA0_XB_HSSIParameter1 0x828\r
+#define rFPGA0_XB_HSSIParameter2 0x82c\r
+\r
+#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch\r
+#define rFPGA0_XCD_SwitchControl 0x85c\r
+\r
+#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter\r
+#define rFPGA0_XCD_RFParameter 0x87c\r
+\r
+#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??\r
+#define rFPGA0_AnalogParameter2 0x884\r
+#define rFPGA0_AnalogParameter3 0x888\r
+#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy\r
+#define rFPGA0_AnalogParameter4 0x88c\r
+#define rFPGA0_XB_LSSIReadBack 0x8a4\r
+#define rFPGA0_XCD_RFPara 0x8b4\r
+\r
+//\r
+// 4. Page9(0x900)\r
+//\r
+#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??\r
+\r
+#define rFPGA1_TxBlock 0x904 // Useless now\r
+#define rFPGA1_DebugSelect 0x908 // Useless now\r
+#define rFPGA1_TxInfo 0x90c // Useless now // Status report??\r
+\r
+//\r
+// PageA(0xA00)\r
+//\r
+#define rCCK0_System 0xa00\r
+#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI\r
+#define rCCK0_DSPParameter2 0xa1c //SQ threshold\r
+#define rCCK0_TxFilter1 0xa20\r
+#define rCCK0_TxFilter2 0xa24\r
+#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3\r
+#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report\r
+\r
+//\r
+// PageB(0xB00)\r
+//\r
+#define rPdp_AntA 0xb00 \r
+#define rPdp_AntA_4 0xb04\r
+#define rConfig_Pmpd_AntA 0xb28\r
+#define rConfig_AntA 0xb68\r
+#define rConfig_AntB 0xb6c\r
+#define rPdp_AntB 0xb70\r
+#define rPdp_AntB_4 0xb74\r
+#define rConfig_Pmpd_AntB 0xb98\r
+#define rAPK 0xbd8\r
+\r
+//\r
+// 6. PageC(0xC00)\r
+//\r
+#define rOFDM0_LSTF 0xc00\r
+\r
+#define rOFDM0_TRxPathEnable 0xc04\r
+#define rOFDM0_TRMuxPar 0xc08\r
+#define rOFDM0_TRSWIsolation 0xc0c\r
+\r
+#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter\r
+#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix\r
+#define rOFDM0_XBRxAFE 0xc18\r
+#define rOFDM0_XBRxIQImbalance 0xc1c\r
+#define rOFDM0_XCRxAFE 0xc20\r
+#define rOFDM0_XCRxIQImbalance 0xc24\r
+#define rOFDM0_XDRxAFE 0xc28\r
+#define rOFDM0_XDRxIQImbalance 0xc2c\r
+\r
+#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain\r
+#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. \r
+#define rOFDM0_RxDetector3 0xc38 //Frame Sync.\r
+#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI\r
+\r
+#define rOFDM0_RxDSP 0xc40 //Rx Sync Path\r
+#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC\r
+#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold\r
+#define rOFDM0_ECCAThreshold 0xc4c // energy CCA\r
+\r
+#define rOFDM0_XAAGCCore1 0xc50 // DIG\r
+#define rOFDM0_XAAGCCore2 0xc54\r
+#define rOFDM0_XBAGCCore1 0xc58\r
+#define rOFDM0_XBAGCCore2 0xc5c\r
+#define rOFDM0_XCAGCCore1 0xc60\r
+#define rOFDM0_XCAGCCore2 0xc64\r
+#define rOFDM0_XDAGCCore1 0xc68\r
+#define rOFDM0_XDAGCCore2 0xc6c\r
+\r
+#define rOFDM0_AGCParameter1 0xc70\r
+#define rOFDM0_AGCParameter2 0xc74\r
+#define rOFDM0_AGCRSSITable 0xc78\r
+#define rOFDM0_HTSTFAGC 0xc7c\r
+\r
+#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG\r
+#define rOFDM0_XATxAFE 0xc84\r
+#define rOFDM0_XBTxIQImbalance 0xc88\r
+#define rOFDM0_XBTxAFE 0xc8c\r
+#define rOFDM0_XCTxIQImbalance 0xc90\r
+#define rOFDM0_XCTxAFE 0xc94\r
+#define rOFDM0_XDTxIQImbalance 0xc98\r
+#define rOFDM0_XDTxAFE 0xc9c\r
+\r
+#define rOFDM0_RxIQExtAnta 0xca0\r
+#define rOFDM0_TxCoeff1 0xca4\r
+#define rOFDM0_TxCoeff2 0xca8\r
+#define rOFDM0_TxCoeff3 0xcac\r
+#define rOFDM0_TxCoeff4 0xcb0\r
+#define rOFDM0_TxCoeff5 0xcb4\r
+#define rOFDM0_TxCoeff6 0xcb8\r
+#define rOFDM0_RxHPParameter 0xce0\r
+#define rOFDM0_TxPseudoNoiseWgt 0xce4\r
+#define rOFDM0_FrameSync 0xcf0\r
+#define rOFDM0_DFSReport 0xcf4\r
+\r
+//\r
+// 7. PageD(0xD00)\r
+//\r
+#define rOFDM1_LSTF 0xd00\r
+#define rOFDM1_TRxPathEnable 0xd04\r
+\r
+//\r
+// 8. PageE(0xE00)\r
+//\r
+#define rTxAGC_A_Rate18_06 0xe00\r
+#define rTxAGC_A_Rate54_24 0xe04\r
+#define rTxAGC_A_CCK1_Mcs32 0xe08\r
+#define rTxAGC_A_Mcs03_Mcs00 0xe10\r
+#define rTxAGC_A_Mcs07_Mcs04 0xe14\r
+#define rTxAGC_A_Mcs11_Mcs08 0xe18\r
+#define rTxAGC_A_Mcs15_Mcs12 0xe1c\r
+\r
+#define rTxAGC_B_Rate18_06 0x830\r
+#define rTxAGC_B_Rate54_24 0x834\r
+#define rTxAGC_B_CCK1_55_Mcs32 0x838\r
+#define rTxAGC_B_Mcs03_Mcs00 0x83c\r
+#define rTxAGC_B_Mcs07_Mcs04 0x848\r
+#define rTxAGC_B_Mcs11_Mcs08 0x84c\r
+#define rTxAGC_B_Mcs15_Mcs12 0x868\r
+#define rTxAGC_B_CCK11_A_CCK2_11 0x86c\r
+\r
+#define rFPGA0_IQK 0xe28\r
+#define rTx_IQK_Tone_A 0xe30\r
+#define rRx_IQK_Tone_A 0xe34\r
+#define rTx_IQK_PI_A 0xe38\r
+#define rRx_IQK_PI_A 0xe3c\r
+\r
+#define rTx_IQK 0xe40\r
+#define rRx_IQK 0xe44\r
+#define rIQK_AGC_Pts 0xe48\r
+#define rIQK_AGC_Rsp 0xe4c\r
+#define rTx_IQK_Tone_B 0xe50\r
+#define rRx_IQK_Tone_B 0xe54\r
+#define rTx_IQK_PI_B 0xe58\r
+#define rRx_IQK_PI_B 0xe5c\r
+#define rIQK_AGC_Cont 0xe60\r
+\r
+#define rBlue_Tooth 0xe6c\r
+#define rRx_Wait_CCA 0xe70\r
+#define rTx_CCK_RFON 0xe74\r
+#define rTx_CCK_BBON 0xe78\r
+#define rTx_OFDM_RFON 0xe7c\r
+#define rTx_OFDM_BBON 0xe80\r
+#define rTx_To_Rx 0xe84\r
+#define rTx_To_Tx 0xe88\r
+#define rRx_CCK 0xe8c\r
+\r
+#define rTx_Power_Before_IQK_A 0xe94\r
+#define rTx_Power_After_IQK_A 0xe9c\r
+\r
+#define rRx_Power_Before_IQK_A 0xea0\r
+#define rRx_Power_Before_IQK_A_2 0xea4\r
+#define rRx_Power_After_IQK_A 0xea8\r
+#define rRx_Power_After_IQK_A_2 0xeac\r
+\r
+#define rTx_Power_Before_IQK_B 0xeb4\r
+#define rTx_Power_After_IQK_B 0xebc\r
+\r
+#define rRx_Power_Before_IQK_B 0xec0\r
+#define rRx_Power_Before_IQK_B_2 0xec4\r
+#define rRx_Power_After_IQK_B 0xec8\r
+#define rRx_Power_After_IQK_B_2 0xecc\r
+\r
+#define rRx_OFDM 0xed0\r
+#define rRx_Wait_RIFS 0xed4\r
+#define rRx_TO_Rx 0xed8\r
+#define rStandby 0xedc\r
+#define rSleep 0xee0\r
+#define rPMPD_ANAEN 0xeec\r
+\r
+\r
+// 2. Page8(0x800)\r
+#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD\r
+#define bJapanMode 0x2\r
+#define bCCKTxSC 0x30\r
+#define bCCKEn 0x1000000\r
+#define bOFDMEn 0x2000000\r
+#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage\r
+#define bXCTxAGC 0xf000\r
+#define bXDTxAGC 0xf0000\r
+\r
+// 4. PageA(0xA00)\r
+#define bCCKBBMode 0x3 // Useless\r
+#define bCCKTxPowerSaving 0x80\r
+#define bCCKRxPowerSaving 0x40\r
+\r
+#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch\r
+\r
+#define bCCKScramble 0x8 // Useless\r
+#define bCCKAntDiversity 0x8000\r
+#define bCCKCarrierRecovery 0x4000\r
+#define bCCKTxRate 0x3000\r
+#define bCCKDCCancel 0x0800\r
+#define bCCKISICancel 0x0400\r
+#define bCCKMatchFilter 0x0200\r
+#define bCCKEqualizer 0x0100\r
+#define bCCKPreambleDetect 0x800000\r
+#define bCCKFastFalseCCA 0x400000\r
+#define bCCKChEstStart 0x300000\r
+#define bCCKCCACount 0x080000\r
+#define bCCKcs_lim 0x070000\r
+#define bCCKBistMode 0x80000000\r
+#define bCCKCCAMask 0x40000000\r
+#define bCCKTxDACPhase 0x4\r
+#define bCCKRxADCPhase 0x20000000 //r_rx_clk\r
+#define bCCKr_cp_mode0 0x0100\r
+#define bCCKTxDCOffset 0xf0\r
+#define bCCKRxDCOffset 0xf\r
+#define bCCKCCAMode 0xc000\r
+#define bCCKFalseCS_lim 0x3f00\r
+#define bCCKCS_ratio 0xc00000\r
+#define bCCKCorgBit_sel 0x300000\r
+#define bCCKPD_lim 0x0f0000\r
+#define bCCKNewCCA 0x80000000\r
+#define bCCKRxHPofIG 0x8000\r
+#define bCCKRxIG 0x7f00\r
+#define bCCKLNAPolarity 0x800000\r
+#define bCCKRx1stGain 0x7f0000\r
+#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity\r
+#define bCCKRxAGCSatLevel 0x1f000000\r
+#define bCCKRxAGCSatCount 0xe0\r
+#define bCCKRxRFSettle 0x1f //AGCsamp_dly\r
+#define bCCKFixedRxAGC 0x8000\r
+//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824\r
+#define bCCKAntennaPolarity 0x2000\r
+#define bCCKTxFilterType 0x0c00\r
+#define bCCKRxAGCReportType 0x0300\r
+#define bCCKRxDAGCEn 0x80000000\r
+#define bCCKRxDAGCPeriod 0x20000000\r
+#define bCCKRxDAGCSatLevel 0x1f000000\r
+#define bCCKTimingRecovery 0x800000\r
+#define bCCKTxC0 0x3f0000\r
+#define bCCKTxC1 0x3f000000\r
+#define bCCKTxC2 0x3f\r
+#define bCCKTxC3 0x3f00\r
+#define bCCKTxC4 0x3f0000\r
+#define bCCKTxC5 0x3f000000\r
+#define bCCKTxC6 0x3f\r
+#define bCCKTxC7 0x3f00\r
+#define bCCKDebugPort 0xff0000\r
+#define bCCKDACDebug 0x0f000000\r
+#define bCCKFalseAlarmEnable 0x8000\r
+#define bCCKFalseAlarmRead 0x4000\r
+#define bCCKTRSSI 0x7f\r
+#define bCCKRxAGCReport 0xfe\r
+#define bCCKRxReport_AntSel 0x80000000\r
+#define bCCKRxReport_MFOff 0x40000000\r
+#define bCCKRxRxReport_SQLoss 0x20000000\r
+#define bCCKRxReport_Pktloss 0x10000000\r
+#define bCCKRxReport_Lockedbit 0x08000000\r
+#define bCCKRxReport_RateError 0x04000000\r
+#define bCCKRxReport_RxRate 0x03000000\r
+#define bCCKRxFACounterLower 0xff\r
+#define bCCKRxFACounterUpper 0xff000000\r
+#define bCCKRxHPAGCStart 0xe000\r
+#define bCCKRxHPAGCFinal 0x1c00 \r
+#define bCCKRxFalseAlarmEnable 0x8000\r
+#define bCCKFACounterFreeze 0x4000 \r
+#define bCCKTxPathSel 0x10000000\r
+#define bCCKDefaultRxPath 0xc000000\r
+#define bCCKOptionRxPath 0x3000000\r
+\r
+// 6. PageE(0xE00)\r
+#define bSTBCEn 0x4 // Useless\r
+#define bAntennaMapping 0x10\r
+#define bNss 0x20\r
+#define bCFOAntSumD 0x200\r
+#define bPHYCounterReset 0x8000000\r
+#define bCFOReportGet 0x4000000\r
+#define bOFDMContinueTx 0x10000000\r
+#define bOFDMSingleCarrier 0x20000000\r
+#define bOFDMSingleTone 0x40000000\r
+\r
+\r
+//\r
+// Other Definition\r
+//\r
+\r
+#define bEnable 0x1 // Useless\r
+#define bDisable 0x0\r
+\r
+//byte endable for srwrite\r
+#define bByte0 0x1 // Useless\r
+#define bByte1 0x2\r
+#define bByte2 0x4\r
+#define bByte3 0x8\r
+#define bWord0 0x3\r
+#define bWord1 0xc\r
+#define bDWord 0xf\r
+\r
+//for PutRegsetting & GetRegSetting BitMask\r
+#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f\r
+#define bMaskByte1 0xff00\r
+#define bMaskByte2 0xff0000\r
+#define bMaskByte3 0xff000000\r
+#define bMaskHWord 0xffff0000\r
+#define bMaskLWord 0x0000ffff\r
+#define bMaskDWord 0xffffffff\r
+#define bMaskH3Bytes 0xffffff00\r
+#define bMask12Bits 0xfff \r
+#define bMaskH4Bits 0xf0000000 \r
+#define bMaskOFDM_D 0xffc00000\r
+#define bMaskCCK 0x3f3f3f3f\r
+\r
+\r
+/*--------------------------Define Parameters-------------------------------*/\r
+\r
+\r
+#endif\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff