--- /dev/null
+/*****************************************************************************\r
+ * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved.\r
+ *\r
+ * Module: __INC_HAL8192SPHYREG_H\r
+ *\r
+ *\r
+ * Note: 1. Define PMAC/BB register map\r
+ * 2. Define RF register map\r
+ * 3. PMAC/BB register bit mask.\r
+ * 4. RF reg bit mask.\r
+ * 5. Other BB/RF relative definition.\r
+ * \r
+ *\r
+ * Export: Constants, macro, functions(API), global variables(None).\r
+ *\r
+ * Abbrev: \r
+ *\r
+ * History:\r
+ * Data Who Remark \r
+ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.\r
+ * 2. Reorganize code architecture.\r
+ * 09/25/2008 MH 1. Add RL6052 register definition\r
+ * \r
+ *****************************************************************************/\r
+#ifndef __INC_HAL8192EPHYREG_H\r
+#define __INC_HAL8192EPHYREG_H\r
+\r
+\r
+/*--------------------------Define Parameters-------------------------------*/\r
+\r
+//============================================================\r
+// 8192S Regsiter offset definition\r
+//============================================================\r
+\r
+//\r
+// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\r
+// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\r
+// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\r
+// 3. RF register 0x00-2E\r
+// 4. Bit Mask for BB/RF register\r
+// 5. Other defintion for BB/RF R/W\r
+//\r
+\r
+\r
+//\r
+// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\r
+// 1. Page1(0x100)\r
+//\r
+#define rPMAC_Reset 0x100\r
+#define rPMAC_TxStart 0x104\r
+#define rPMAC_TxLegacySIG 0x108\r
+#define rPMAC_TxHTSIG1 0x10c\r
+#define rPMAC_TxHTSIG2 0x110\r
+#define rPMAC_PHYDebug 0x114\r
+#define rPMAC_TxPacketNum 0x118\r
+#define rPMAC_TxIdle 0x11c\r
+#define rPMAC_TxMACHeader0 0x120\r
+#define rPMAC_TxMACHeader1 0x124\r
+#define rPMAC_TxMACHeader2 0x128\r
+#define rPMAC_TxMACHeader3 0x12c\r
+#define rPMAC_TxMACHeader4 0x130\r
+#define rPMAC_TxMACHeader5 0x134\r
+#define rPMAC_TxDataType 0x138\r
+#define rPMAC_TxRandomSeed 0x13c\r
+#define rPMAC_CCKPLCPPreamble 0x140\r
+#define rPMAC_CCKPLCPHeader 0x144\r
+#define rPMAC_CCKCRC16 0x148\r
+#define rPMAC_OFDMRxCRC32OK 0x170\r
+#define rPMAC_OFDMRxCRC32Er 0x174\r
+#define rPMAC_OFDMRxParityEr 0x178\r
+#define rPMAC_OFDMRxCRC8Er 0x17c\r
+#define rPMAC_CCKCRxRC16Er 0x180\r
+#define rPMAC_CCKCRxRC32Er 0x184\r
+#define rPMAC_CCKCRxRC32OK 0x188\r
+#define rPMAC_TxStatus 0x18c\r
+\r
+\r
+//\r
+// 3. Page8(0x800)\r
+//\r
+#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??\r
+\r
+#define rFPGA0_TxInfo 0x804 // Status report??\r
+#define rFPGA0_PSDFunction 0x808\r
+\r
+#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?\r
+\r
+#define rFPGA0_RFTiming1 0x810 // Useless now\r
+#define rFPGA0_RFTiming2 0x814\r
+\r
+#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register\r
+#define rFPGA0_XA_HSSIParameter2 0x824\r
+#define rFPGA0_XB_HSSIParameter1 0x828\r
+#define rFPGA0_XB_HSSIParameter2 0x82c\r
+\r
+#define rFPGA0_XA_LSSIParameter 0x840\r
+#define rFPGA0_XB_LSSIParameter 0x844\r
+\r
+#define rFPGA0_RFWakeUpParameter 0x850 // Useless now\r
+#define rFPGA0_RFSleepUpParameter 0x854\r
+\r
+#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch\r
+#define rFPGA0_XCD_SwitchControl 0x85c\r
+\r
+#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch\r
+#define rFPGA0_XB_RFInterfaceOE 0x864\r
+\r
+#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control\r
+#define rFPGA0_XCD_RFInterfaceSW 0x874\r
+\r
+#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter\r
+#define rFPGA0_XCD_RFParameter 0x87c\r
+\r
+#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??\r
+#define rFPGA0_AnalogParameter2 0x884\r
+#define rFPGA0_AnalogParameter3 0x888\r
+#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy\r
+#define rFPGA0_AnalogParameter4 0x88c\r
+\r
+#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback\r
+#define rFPGA0_XB_LSSIReadBack 0x8a4\r
+#define rFPGA0_XC_LSSIReadBack 0x8a8\r
+#define rFPGA0_XD_LSSIReadBack 0x8ac\r
+\r
+#define rFPGA0_PSDReport 0x8b4 // Useless now\r
+#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback\r
+#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback\r
+#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value\r
+#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now\r
+\r
+//\r
+// 4. Page9(0x900)\r
+//\r
+#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??\r
+\r
+#define rFPGA1_TxBlock 0x904 // Useless now\r
+#define rFPGA1_DebugSelect 0x908 // Useless now\r
+#define rFPGA1_TxInfo 0x90c // Useless now // Status report??\r
+\r
+//\r
+// 5. PageA(0xA00)\r
+//\r
+// Set Control channel to upper or lower. These settings are required only for 40MHz\r
+#define rCCK0_System 0xa00\r
+\r
+#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI\r
+#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain\r
+\r
+#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series\r
+#define rCCK0_RxAGC2 0xa10 //AGC & DAGC\r
+\r
+#define rCCK0_RxHP 0xa14\r
+\r
+#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold\r
+#define rCCK0_DSPParameter2 0xa1c //SQ threshold\r
+\r
+#define rCCK0_TxFilter1 0xa20\r
+#define rCCK0_TxFilter2 0xa24\r
+#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3\r
+#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report\r
+#define rCCK0_TRSSIReport 0xa50\r
+#define rCCK0_RxReport 0xa54 //0xa57\r
+#define rCCK0_FACounterLower 0xa5c //0xa5b\r
+#define rCCK0_FACounterUpper 0xa58 //0xa5c\r
+\r
+//\r
+// PageB(0xB00)\r
+//\r
+#define rPdp_AntA 0xb00 \r
+#define rPdp_AntA_4 0xb04\r
+#define rConfig_Pmpd_AntA 0xb28\r
+#define rConfig_ram64x16 0xb2c\r
+\r
+#define rConfig_AntA 0xb68\r
+#define rConfig_AntB 0xb6c\r
+#define rPdp_AntB 0xb70\r
+#define rPdp_AntB_4 0xb74\r
+#define rConfig_Pmpd_AntB 0xb98\r
+#define rAPK 0xbd8\r
+\r
+\r
+\r
+//\r
+// 6. PageC(0xC00)\r
+//\r
+#define rOFDM0_LSTF 0xc00\r
+\r
+#define rOFDM0_TRxPathEnable 0xc04\r
+#define rOFDM0_TRMuxPar 0xc08\r
+#define rOFDM0_TRSWIsolation 0xc0c\r
+\r
+#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter\r
+#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix\r
+#define rOFDM0_XBRxAFE 0xc18\r
+#define rOFDM0_XBRxIQImbalance 0xc1c\r
+#define rOFDM0_XCRxAFE 0xc20\r
+#define rOFDM0_XCRxIQImbalance 0xc24\r
+#define rOFDM0_XDRxAFE 0xc28\r
+#define rOFDM0_XDRxIQImbalance 0xc2c\r
+\r
+#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain\r
+#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. \r
+#define rOFDM0_RxDetector3 0xc38 //Frame Sync.\r
+#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI\r
+\r
+#define rOFDM0_RxDSP 0xc40 //Rx Sync Path\r
+#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC\r
+#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold\r
+#define rOFDM0_ECCAThreshold 0xc4c // energy CCA\r
+\r
+#define rOFDM0_XAAGCCore1 0xc50 // DIG\r
+#define rOFDM0_XAAGCCore2 0xc54\r
+#define rOFDM0_XBAGCCore1 0xc58\r
+#define rOFDM0_XBAGCCore2 0xc5c\r
+#define rOFDM0_XCAGCCore1 0xc60\r
+#define rOFDM0_XCAGCCore2 0xc64\r
+#define rOFDM0_XDAGCCore1 0xc68\r
+#define rOFDM0_XDAGCCore2 0xc6c\r
+\r
+#define rOFDM0_AGCParameter1 0xc70\r
+#define rOFDM0_AGCParameter2 0xc74\r
+#define rOFDM0_AGCRSSITable 0xc78\r
+#define rOFDM0_HTSTFAGC 0xc7c\r
+\r
+#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG\r
+#define rOFDM0_XATxAFE 0xc84\r
+#define rOFDM0_XBTxIQImbalance 0xc88\r
+#define rOFDM0_XBTxAFE 0xc8c\r
+#define rOFDM0_XCTxIQImbalance 0xc90\r
+#define rOFDM0_XCTxAFE 0xc94\r
+#define rOFDM0_XDTxIQImbalance 0xc98\r
+#define rOFDM0_XDTxAFE 0xc9c\r
+\r
+#define rOFDM0_RxIQExtAnta 0xca0\r
+#define rOFDM0_TxCoeff1 0xca4\r
+#define rOFDM0_TxCoeff2 0xca8\r
+#define rOFDM0_TxCoeff3 0xcac\r
+#define rOFDM0_TxCoeff4 0xcb0\r
+#define rOFDM0_TxCoeff5 0xcb4\r
+#define rOFDM0_RxHPParameter 0xce0\r
+#define rOFDM0_TxPseudoNoiseWgt 0xce4\r
+#define rOFDM0_FrameSync 0xcf0\r
+#define rOFDM0_DFSReport 0xcf4\r
+\r
+\r
+//\r
+// 7. PageD(0xD00)\r
+//\r
+#define rOFDM1_LSTF 0xd00\r
+#define rOFDM1_TRxPathEnable 0xd04\r
+\r
+#define rOFDM1_CFO 0xd08 // No setting now\r
+#define rOFDM1_CSI1 0xd10\r
+#define rOFDM1_SBD 0xd14\r
+#define rOFDM1_CSI2 0xd18\r
+#define rOFDM1_CFOTracking 0xd2c\r
+#define rOFDM1_TRxMesaure1 0xd34\r
+#define rOFDM1_IntfDet 0xd3c\r
+#define rOFDM1_PseudoNoiseStateAB 0xd50\r
+#define rOFDM1_PseudoNoiseStateCD 0xd54\r
+#define rOFDM1_RxPseudoNoiseWgt 0xd58\r
+\r
+#define rOFDM_PHYCounter1 0xda0 //cca, parity fail\r
+#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail\r
+#define rOFDM_PHYCounter3 0xda8 //MCS not support\r
+\r
+#define rOFDM_ShortCFOAB 0xdac // No setting now\r
+#define rOFDM_ShortCFOCD 0xdb0\r
+#define rOFDM_LongCFOAB 0xdb4\r
+#define rOFDM_LongCFOCD 0xdb8\r
+#define rOFDM_TailCFOAB 0xdbc\r
+#define rOFDM_TailCFOCD 0xdc0\r
+#define rOFDM_PWMeasure1 0xdc4\r
+#define rOFDM_PWMeasure2 0xdc8\r
+#define rOFDM_BWReport 0xdcc\r
+#define rOFDM_AGCReport 0xdd0\r
+#define rOFDM_RxSNR 0xdd4\r
+#define rOFDM_RxEVMCSI 0xdd8\r
+#define rOFDM_SIGReport 0xddc\r
+\r
+\r
+//\r
+// 8. PageE(0xE00)\r
+//\r
+#define rTxAGC_A_Rate18_06 0xe00\r
+#define rTxAGC_A_Rate54_24 0xe04\r
+#define rTxAGC_A_CCK1_Mcs32 0xe08\r
+#define rTxAGC_A_Mcs03_Mcs00 0xe10\r
+#define rTxAGC_A_Mcs07_Mcs04 0xe14\r
+#define rTxAGC_A_Mcs11_Mcs08 0xe18\r
+#define rTxAGC_A_Mcs15_Mcs12 0xe1c\r
+\r
+#define rTxAGC_B_Rate18_06 0x830\r
+#define rTxAGC_B_Rate54_24 0x834\r
+#define rTxAGC_B_CCK1_55_Mcs32 0x838\r
+#define rTxAGC_B_Mcs03_Mcs00 0x83c\r
+#define rTxAGC_B_Mcs07_Mcs04 0x848\r
+#define rTxAGC_B_Mcs11_Mcs08 0x84c\r
+#define rTxAGC_B_Mcs15_Mcs12 0x868\r
+#define rTxAGC_B_CCK11_A_CCK2_11 0x86c\r
+\r
+#define rFPGA0_IQK 0xe28\r
+#define rTx_IQK_Tone_A 0xe30\r
+#define rRx_IQK_Tone_A 0xe34\r
+#define rTx_IQK_PI_A 0xe38\r
+#define rRx_IQK_PI_A 0xe3c\r
+\r
+#define rTx_IQK 0xe40\r
+#define rRx_IQK 0xe44\r
+#define rIQK_AGC_Pts 0xe48\r
+#define rIQK_AGC_Rsp 0xe4c\r
+#define rTx_IQK_Tone_B 0xe50\r
+#define rRx_IQK_Tone_B 0xe54\r
+#define rTx_IQK_PI_B 0xe58\r
+#define rRx_IQK_PI_B 0xe5c\r
+#define rIQK_AGC_Cont 0xe60\r
+\r
+#define rBlue_Tooth 0xe6c\r
+#define rRx_Wait_CCA 0xe70\r
+#define rTx_CCK_RFON 0xe74\r
+#define rTx_CCK_BBON 0xe78\r
+#define rTx_OFDM_RFON 0xe7c\r
+#define rTx_OFDM_BBON 0xe80\r
+#define rTx_To_Rx 0xe84\r
+#define rTx_To_Tx 0xe88\r
+#define rRx_CCK 0xe8c\r
+\r
+#define rTx_Power_Before_IQK_A 0xe94\r
+#define rTx_Power_After_IQK_A 0xe9c\r
+\r
+#define rRx_Power_Before_IQK_A 0xea0\r
+#define rRx_Power_Before_IQK_A_2 0xea4\r
+#define rRx_Power_After_IQK_A 0xea8\r
+#define rRx_Power_After_IQK_A_2 0xeac\r
+\r
+#define rTx_Power_Before_IQK_B 0xeb4\r
+#define rTx_Power_After_IQK_B 0xebc\r
+\r
+#define rRx_Power_Before_IQK_B 0xec0\r
+#define rRx_Power_Before_IQK_B_2 0xec4\r
+#define rRx_Power_After_IQK_B 0xec8\r
+#define rRx_Power_After_IQK_B_2 0xecc\r
+\r
+#define rRx_OFDM 0xed0\r
+#define rRx_Wait_RIFS 0xed4\r
+#define rRx_TO_Rx 0xed8\r
+#define rStandby 0xedc\r
+#define rSleep 0xee0\r
+#define rPMPD_ANAEN 0xeec\r
+\r
+//\r
+// 7. RF Register 0x00-0x2E (RF 8256)\r
+// RF-0222D 0x00-3F\r
+//\r
+//Zebra1\r
+#define rZebra1_HSSIEnable 0x0 // Useless now\r
+#define rZebra1_TRxEnable1 0x1\r
+#define rZebra1_TRxEnable2 0x2\r
+#define rZebra1_AGC 0x4\r
+#define rZebra1_ChargePump 0x5\r
+#define rZebra1_Channel 0x7 // RF channel switch\r
+\r
+//#endif\r
+#define rZebra1_TxGain 0x8 // Useless now\r
+#define rZebra1_TxLPF 0x9\r
+#define rZebra1_RxLPF 0xb\r
+#define rZebra1_RxHPFCorner 0xc\r
+\r
+//Zebra4\r
+#define rGlobalCtrl 0 // Useless now\r
+#define rRTL8256_TxLPF 19\r
+#define rRTL8256_RxLPF 11\r
+\r
+//RTL8258\r
+#define rRTL8258_TxLPF 0x11 // Useless now\r
+#define rRTL8258_RxLPF 0x13\r
+#define rRTL8258_RSSILPF 0xa\r
+\r
+//\r
+// RL6052 Register definition\r
+//\r
+#define RF_AC 0x00 // \r
+\r
+#define RF_IQADJ_G1 0x01 // \r
+#define RF_IQADJ_G2 0x02 // \r
+\r
+#define RF_POW_TRSW 0x05 // \r
+\r
+#define RF_GAIN_RX 0x06 // \r
+#define RF_GAIN_TX 0x07 // \r
+\r
+#define RF_TXM_IDAC 0x08 // \r
+#define RF_IPA_G 0x09 // \r
+#define RF_TXBIAS_G 0x0A\r
+#define RF_TXPA_AG 0x0B\r
+#define RF_IPA_A 0x0C // \r
+#define RF_TXBIAS_A 0x0D\r
+#define RF_BS_PA_APSET_G9_G11 0x0E\r
+#define RF_BS_IQGEN 0x0F // \r
+\r
+#define RF_MODE1 0x10 // \r
+#define RF_MODE2 0x11 // \r
+\r
+#define RF_RX_AGC_HP 0x12 // \r
+#define RF_TX_AGC 0x13 // \r
+#define RF_BIAS 0x14 // \r
+#define RF_IPA 0x15 // \r
+#define RF_TXBIAS 0x16\r
+#define RF_POW_ABILITY 0x17 // \r
+#define RF_CHNLBW 0x18 // RF channel and BW switch\r
+#define RF_TOP 0x19 // \r
+\r
+#define RF_RX_G1 0x1A // \r
+#define RF_RX_G2 0x1B // \r
+\r
+#define RF_RX_BB2 0x1C // \r
+#define RF_RX_BB1 0x1D // \r
+\r
+#define RF_RCK1 0x1E // \r
+#define RF_RCK2 0x1F // \r
+\r
+#define RF_TX_G1 0x20 // \r
+#define RF_TX_G2 0x21 // \r
+#define RF_TX_G3 0x22 // \r
+\r
+#define RF_TX_BB1 0x23 // \r
+\r
+#define RF_T_METER_8192E 0x42 // \r
+#define RF_T_METER_88E 0x42 //\r
+#define RF_T_METER 0x24 // \r
+\r
+//#endif\r
+\r
+#define RF_SYN_G1 0x25 // RF TX Power control\r
+#define RF_SYN_G2 0x26 // RF TX Power control\r
+#define RF_SYN_G3 0x27 // RF TX Power control\r
+#define RF_SYN_G4 0x28 // RF TX Power control\r
+#define RF_SYN_G5 0x29 // RF TX Power control\r
+#define RF_SYN_G6 0x2A // RF TX Power control\r
+#define RF_SYN_G7 0x2B // RF TX Power control\r
+#define RF_SYN_G8 0x2C // RF TX Power control\r
+\r
+#define RF_RCK_OS 0x30 // RF TX PA control\r
+#define RF_TXPA_G1 0x31 // RF TX PA control\r
+#define RF_TXPA_G2 0x32 // RF TX PA control\r
+#define RF_TXPA_G3 0x33 // RF TX PA control\r
+#define RF_TX_BIAS_A 0x35\r
+#define RF_TX_BIAS_D 0x36\r
+#define RF_LOBF_9 0x38\r
+#define RF_RXRF_A3 0x3C // \r
+#define RF_TRSW 0x3F\r
+\r
+#define RF_TXRF_A2 0x41\r
+#define RF_TXPA_G4 0x46 \r
+#define RF_TXPA_A4 0x4B \r
+#define RF_0x52 0x52\r
+#define RF_LDO 0xB1\r
+#define RF_WE_LUT 0xEF \r
+\r
+\r
+//\r
+//Bit Mask\r
+//\r
+// 1. Page1(0x100)\r
+#define bBBResetB 0x100 // Useless now?\r
+#define bGlobalResetB 0x200\r
+#define bOFDMTxStart 0x4\r
+#define bCCKTxStart 0x8\r
+#define bCRC32Debug 0x100\r
+#define bPMACLoopback 0x10\r
+#define bTxLSIG 0xffffff\r
+#define bOFDMTxRate 0xf\r
+#define bOFDMTxReserved 0x10\r
+#define bOFDMTxLength 0x1ffe0\r
+#define bOFDMTxParity 0x20000\r
+#define bTxHTSIG1 0xffffff\r
+#define bTxHTMCSRate 0x7f\r
+#define bTxHTBW 0x80\r
+#define bTxHTLength 0xffff00\r
+#define bTxHTSIG2 0xffffff\r
+#define bTxHTSmoothing 0x1\r
+#define bTxHTSounding 0x2\r
+#define bTxHTReserved 0x4\r
+#define bTxHTAggreation 0x8\r
+#define bTxHTSTBC 0x30\r
+#define bTxHTAdvanceCoding 0x40\r
+#define bTxHTShortGI 0x80\r
+#define bTxHTNumberHT_LTF 0x300\r
+#define bTxHTCRC8 0x3fc00\r
+#define bCounterReset 0x10000\r
+#define bNumOfOFDMTx 0xffff\r
+#define bNumOfCCKTx 0xffff0000\r
+#define bTxIdleInterval 0xffff\r
+#define bOFDMService 0xffff0000\r
+#define bTxMACHeader 0xffffffff\r
+#define bTxDataInit 0xff\r
+#define bTxHTMode 0x100\r
+#define bTxDataType 0x30000\r
+#define bTxRandomSeed 0xffffffff\r
+#define bCCKTxPreamble 0x1\r
+#define bCCKTxSFD 0xffff0000\r
+#define bCCKTxSIG 0xff\r
+#define bCCKTxService 0xff00\r
+#define bCCKLengthExt 0x8000\r
+#define bCCKTxLength 0xffff0000\r
+#define bCCKTxCRC16 0xffff\r
+#define bCCKTxStatus 0x1\r
+#define bOFDMTxStatus 0x2\r
+\r
+#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))\r
+#define RF_TX_GAIN_OFFSET_8192E(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))\r
+\r
+\r
+// 2. Page8(0x800)\r
+#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD\r
+#define bJapanMode 0x2\r
+#define bCCKTxSC 0x30\r
+#define bCCKEn 0x1000000\r
+#define bOFDMEn 0x2000000\r
+\r
+#define bOFDMRxADCPhase 0x10000 // Useless now\r
+#define bOFDMTxDACPhase 0x40000\r
+#define bXATxAGC 0x3f\r
+\r
+#define bAntennaSelect 0x0300\r
+\r
+#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage\r
+#define bXCTxAGC 0xf000\r
+#define bXDTxAGC 0xf0000\r
+ \r
+#define bPAStart 0xf0000000 // Useless now\r
+#define bTRStart 0x00f00000\r
+#define bRFStart 0x0000f000\r
+#define bBBStart 0x000000f0\r
+#define bBBCCKStart 0x0000000f\r
+#define bPAEnd 0xf //Reg0x814\r
+#define bTREnd 0x0f000000\r
+#define bRFEnd 0x000f0000\r
+#define bCCAMask 0x000000f0 //T2R\r
+#define bR2RCCAMask 0x00000f00\r
+#define bHSSI_R2TDelay 0xf8000000\r
+#define bHSSI_T2RDelay 0xf80000\r
+#define bContTxHSSI 0x400 //chane gain at continue Tx\r
+#define bIGFromCCK 0x200\r
+#define bAGCAddress 0x3f\r
+#define bRxHPTx 0x7000\r
+#define bRxHPT2R 0x38000\r
+#define bRxHPCCKIni 0xc0000\r
+#define bAGCTxCode 0xc00000\r
+#define bAGCRxCode 0x300000\r
+\r
+#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1\r
+#define b3WireAddressLength 0x400\r
+\r
+#define b3WireRFPowerDown 0x1 // Useless now\r
+//#define bHWSISelect 0x8\r
+#define b5GPAPEPolarity 0x40000000\r
+#define b2GPAPEPolarity 0x80000000\r
+#define bRFSW_TxDefaultAnt 0x3\r
+#define bRFSW_TxOptionAnt 0x30\r
+#define bRFSW_RxDefaultAnt 0x300\r
+#define bRFSW_RxOptionAnt 0x3000\r
+#define bRFSI_3WireData 0x1\r
+#define bRFSI_3WireClock 0x2\r
+#define bRFSI_3WireLoad 0x4\r
+#define bRFSI_3WireRW 0x8\r
+#define bRFSI_3Wire 0xf\r
+\r
+#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW\r
+\r
+#define bRFSI_TRSW 0x20 // Useless now\r
+#define bRFSI_TRSWB 0x40\r
+#define bRFSI_ANTSW 0x100\r
+#define bRFSI_ANTSWB 0x200\r
+#define bRFSI_PAPE 0x400\r
+#define bRFSI_PAPE5G 0x800 \r
+#define bBandSelect 0x1\r
+#define bHTSIG2_GI 0x80\r
+#define bHTSIG2_Smoothing 0x01\r
+#define bHTSIG2_Sounding 0x02\r
+#define bHTSIG2_Aggreaton 0x08\r
+#define bHTSIG2_STBC 0x30\r
+#define bHTSIG2_AdvCoding 0x40\r
+#define bHTSIG2_NumOfHTLTF 0x300\r
+#define bHTSIG2_CRC8 0x3fc\r
+#define bHTSIG1_MCS 0x7f\r
+#define bHTSIG1_BandWidth 0x80\r
+#define bHTSIG1_HTLength 0xffff\r
+#define bLSIG_Rate 0xf\r
+#define bLSIG_Reserved 0x10\r
+#define bLSIG_Length 0x1fffe\r
+#define bLSIG_Parity 0x20\r
+#define bCCKRxPhase 0x4\r
+\r
+#define bLSSIReadAddress 0x7f800000 // T65 RF\r
+\r
+#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal\r
+\r
+#define bLSSIReadBackData 0xfffff // T65 RF\r
+\r
+#define bLSSIReadOKFlag 0x1000 // Useless now\r
+#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz \r
+#define bRegulator0Standby 0x1\r
+#define bRegulatorPLLStandby 0x2\r
+#define bRegulator1Standby 0x4\r
+#define bPLLPowerUp 0x8\r
+#define bDPLLPowerUp 0x10\r
+#define bDA10PowerUp 0x20\r
+#define bAD7PowerUp 0x200\r
+#define bDA6PowerUp 0x2000\r
+#define bXtalPowerUp 0x4000\r
+#define b40MDClkPowerUP 0x8000\r
+#define bDA6DebugMode 0x20000\r
+#define bDA6Swing 0x380000\r
+\r
+#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ\r
+\r
+#define b80MClkDelay 0x18000000 // Useless\r
+#define bAFEWatchDogEnable 0x20000000\r
+\r
+#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap\r
+#define bXtalCap23 0x3\r
+#define bXtalCap92x 0x0f000000\r
+#define bXtalCap 0x0f000000\r
+\r
+#define bIntDifClkEnable 0x400 // Useless\r
+#define bExtSigClkEnable 0x800\r
+#define bBandgapMbiasPowerUp 0x10000\r
+#define bAD11SHGain 0xc0000\r
+#define bAD11InputRange 0x700000\r
+#define bAD11OPCurrent 0x3800000\r
+#define bIPathLoopback 0x4000000\r
+#define bQPathLoopback 0x8000000\r
+#define bAFELoopback 0x10000000\r
+#define bDA10Swing 0x7e0\r
+#define bDA10Reverse 0x800\r
+#define bDAClkSource 0x1000\r
+#define bAD7InputRange 0x6000\r
+#define bAD7Gain 0x38000\r
+#define bAD7OutputCMMode 0x40000\r
+#define bAD7InputCMMode 0x380000\r
+#define bAD7Current 0xc00000\r
+#define bRegulatorAdjust 0x7000000\r
+#define bAD11PowerUpAtTx 0x1\r
+#define bDA10PSAtTx 0x10\r
+#define bAD11PowerUpAtRx 0x100\r
+#define bDA10PSAtRx 0x1000 \r
+#define bCCKRxAGCFormat 0x200 \r
+#define bPSDFFTSamplepPoint 0xc000\r
+#define bPSDAverageNum 0x3000\r
+#define bIQPathControl 0xc00\r
+#define bPSDFreq 0x3ff\r
+#define bPSDAntennaPath 0x30\r
+#define bPSDIQSwitch 0x40\r
+#define bPSDRxTrigger 0x400000\r
+#define bPSDTxTrigger 0x80000000\r
+#define bPSDSineToneScale 0x7f000000\r
+#define bPSDReport 0xffff\r
+\r
+// 3. Page9(0x900)\r
+#define bOFDMTxSC 0x30000000 // Useless\r
+#define bCCKTxOn 0x1\r
+#define bOFDMTxOn 0x2\r
+#define bDebugPage 0xfff //reset debug page and also HWord, LWord\r
+#define bDebugItem 0xff //reset debug page and LWord\r
+#define bAntL 0x10\r
+#define bAntNonHT 0x100\r
+#define bAntHT1 0x1000\r
+#define bAntHT2 0x10000\r
+#define bAntHT1S1 0x100000\r
+#define bAntNonHTS1 0x1000000\r
+\r
+// 4. PageA(0xA00)\r
+#define bCCKBBMode 0x3 // Useless\r
+#define bCCKTxPowerSaving 0x80\r
+#define bCCKRxPowerSaving 0x40\r
+\r
+#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch\r
+\r
+#define bCCKScramble 0x8 // Useless\r
+#define bCCKAntDiversity 0x8000\r
+#define bCCKCarrierRecovery 0x4000\r
+#define bCCKTxRate 0x3000\r
+#define bCCKDCCancel 0x0800\r
+#define bCCKISICancel 0x0400\r
+#define bCCKMatchFilter 0x0200\r
+#define bCCKEqualizer 0x0100\r
+#define bCCKPreambleDetect 0x800000\r
+#define bCCKFastFalseCCA 0x400000\r
+#define bCCKChEstStart 0x300000\r
+#define bCCKCCACount 0x080000\r
+#define bCCKcs_lim 0x070000\r
+#define bCCKBistMode 0x80000000\r
+#define bCCKCCAMask 0x40000000\r
+#define bCCKTxDACPhase 0x4\r
+#define bCCKRxADCPhase 0x20000000 //r_rx_clk\r
+#define bCCKr_cp_mode0 0x0100\r
+#define bCCKTxDCOffset 0xf0\r
+#define bCCKRxDCOffset 0xf\r
+#define bCCKCCAMode 0xc000\r
+#define bCCKFalseCS_lim 0x3f00\r
+#define bCCKCS_ratio 0xc00000\r
+#define bCCKCorgBit_sel 0x300000\r
+#define bCCKPD_lim 0x0f0000\r
+#define bCCKNewCCA 0x80000000\r
+#define bCCKRxHPofIG 0x8000\r
+#define bCCKRxIG 0x7f00\r
+#define bCCKLNAPolarity 0x800000\r
+#define bCCKRx1stGain 0x7f0000\r
+#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity\r
+#define bCCKRxAGCSatLevel 0x1f000000\r
+#define bCCKRxAGCSatCount 0xe0\r
+#define bCCKRxRFSettle 0x1f //AGCsamp_dly\r
+#define bCCKFixedRxAGC 0x8000\r
+//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824\r
+#define bCCKAntennaPolarity 0x2000\r
+#define bCCKTxFilterType 0x0c00\r
+#define bCCKRxAGCReportType 0x0300\r
+#define bCCKRxDAGCEn 0x80000000\r
+#define bCCKRxDAGCPeriod 0x20000000\r
+#define bCCKRxDAGCSatLevel 0x1f000000\r
+#define bCCKTimingRecovery 0x800000\r
+#define bCCKTxC0 0x3f0000\r
+#define bCCKTxC1 0x3f000000\r
+#define bCCKTxC2 0x3f\r
+#define bCCKTxC3 0x3f00\r
+#define bCCKTxC4 0x3f0000\r
+#define bCCKTxC5 0x3f000000\r
+#define bCCKTxC6 0x3f\r
+#define bCCKTxC7 0x3f00\r
+#define bCCKDebugPort 0xff0000\r
+#define bCCKDACDebug 0x0f000000\r
+#define bCCKFalseAlarmEnable 0x8000\r
+#define bCCKFalseAlarmRead 0x4000\r
+#define bCCKTRSSI 0x7f\r
+#define bCCKRxAGCReport 0xfe\r
+#define bCCKRxReport_AntSel 0x80000000\r
+#define bCCKRxReport_MFOff 0x40000000\r
+#define bCCKRxRxReport_SQLoss 0x20000000\r
+#define bCCKRxReport_Pktloss 0x10000000\r
+#define bCCKRxReport_Lockedbit 0x08000000\r
+#define bCCKRxReport_RateError 0x04000000\r
+#define bCCKRxReport_RxRate 0x03000000\r
+#define bCCKRxFACounterLower 0xff\r
+#define bCCKRxFACounterUpper 0xff000000\r
+#define bCCKRxHPAGCStart 0xe000\r
+#define bCCKRxHPAGCFinal 0x1c00 \r
+#define bCCKRxFalseAlarmEnable 0x8000\r
+#define bCCKFACounterFreeze 0x4000 \r
+#define bCCKTxPathSel 0x10000000\r
+#define bCCKDefaultRxPath 0xc000000\r
+#define bCCKOptionRxPath 0x3000000\r
+\r
+// 5. PageC(0xC00)\r
+#define bNumOfSTF 0x3 // Useless\r
+#define bShift_L 0xc0\r
+#define bGI_TH 0xc\r
+#define bRxPathA 0x1\r
+#define bRxPathB 0x2\r
+#define bRxPathC 0x4\r
+#define bRxPathD 0x8\r
+#define bTxPathA 0x1\r
+#define bTxPathB 0x2\r
+#define bTxPathC 0x4\r
+#define bTxPathD 0x8\r
+#define bTRSSIFreq 0x200\r
+#define bADCBackoff 0x3000\r
+#define bDFIRBackoff 0xc000\r
+#define bTRSSILatchPhase 0x10000\r
+#define bRxIDCOffset 0xff\r
+#define bRxQDCOffset 0xff00\r
+#define bRxDFIRMode 0x1800000\r
+#define bRxDCNFType 0xe000000\r
+#define bRXIQImb_A 0x3ff\r
+#define bRXIQImb_B 0xfc00\r
+#define bRXIQImb_C 0x3f0000\r
+#define bRXIQImb_D 0xffc00000\r
+#define bDC_dc_Notch 0x60000\r
+#define bRxNBINotch 0x1f000000\r
+#define bPD_TH 0xf\r
+#define bPD_TH_Opt2 0xc000\r
+#define bPWED_TH 0x700\r
+#define bIfMF_Win_L 0x800\r
+#define bPD_Option 0x1000\r
+#define bMF_Win_L 0xe000\r
+#define bBW_Search_L 0x30000\r
+#define bwin_enh_L 0xc0000\r
+#define bBW_TH 0x700000\r
+#define bED_TH2 0x3800000\r
+#define bBW_option 0x4000000\r
+#define bRatio_TH 0x18000000\r
+#define bWindow_L 0xe0000000\r
+#define bSBD_Option 0x1\r
+#define bFrame_TH 0x1c\r
+#define bFS_Option 0x60\r
+#define bDC_Slope_check 0x80\r
+#define bFGuard_Counter_DC_L 0xe00\r
+#define bFrame_Weight_Short 0x7000\r
+#define bSub_Tune 0xe00000\r
+#define bFrame_DC_Length 0xe000000\r
+#define bSBD_start_offset 0x30000000\r
+#define bFrame_TH_2 0x7\r
+#define bFrame_GI2_TH 0x38\r
+#define bGI2_Sync_en 0x40\r
+#define bSarch_Short_Early 0x300\r
+#define bSarch_Short_Late 0xc00\r
+#define bSarch_GI2_Late 0x70000\r
+#define bCFOAntSum 0x1\r
+#define bCFOAcc 0x2\r
+#define bCFOStartOffset 0xc\r
+#define bCFOLookBack 0x70\r
+#define bCFOSumWeight 0x80\r
+#define bDAGCEnable 0x10000\r
+#define bTXIQImb_A 0x3ff\r
+#define bTXIQImb_B 0xfc00\r
+#define bTXIQImb_C 0x3f0000\r
+#define bTXIQImb_D 0xffc00000\r
+#define bTxIDCOffset 0xff\r
+#define bTxQDCOffset 0xff00\r
+#define bTxDFIRMode 0x10000\r
+#define bTxPesudoNoiseOn 0x4000000\r
+#define bTxPesudoNoise_A 0xff\r
+#define bTxPesudoNoise_B 0xff00\r
+#define bTxPesudoNoise_C 0xff0000\r
+#define bTxPesudoNoise_D 0xff000000\r
+#define bCCADropOption 0x20000\r
+#define bCCADropThres 0xfff00000\r
+#define bEDCCA_H 0xf\r
+#define bEDCCA_L 0xf0\r
+#define bLambda_ED 0x300\r
+#define bRxInitialGain 0x7f\r
+#define bRxAntDivEn 0x80\r
+#define bRxAGCAddressForLNA 0x7f00\r
+#define bRxHighPowerFlow 0x8000\r
+#define bRxAGCFreezeThres 0xc0000\r
+#define bRxFreezeStep_AGC1 0x300000\r
+#define bRxFreezeStep_AGC2 0xc00000\r
+#define bRxFreezeStep_AGC3 0x3000000\r
+#define bRxFreezeStep_AGC0 0xc000000\r
+#define bRxRssi_Cmp_En 0x10000000\r
+#define bRxQuickAGCEn 0x20000000\r
+#define bRxAGCFreezeThresMode 0x40000000\r
+#define bRxOverFlowCheckType 0x80000000\r
+#define bRxAGCShift 0x7f\r
+#define bTRSW_Tri_Only 0x80\r
+#define bPowerThres 0x300\r
+#define bRxAGCEn 0x1\r
+#define bRxAGCTogetherEn 0x2\r
+#define bRxAGCMin 0x4\r
+#define bRxHP_Ini 0x7\r
+#define bRxHP_TRLNA 0x70\r
+#define bRxHP_RSSI 0x700\r
+#define bRxHP_BBP1 0x7000\r
+#define bRxHP_BBP2 0x70000\r
+#define bRxHP_BBP3 0x700000\r
+#define bRSSI_H 0x7f0000 //the threshold for high power\r
+#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity\r
+#define bRxSettle_TRSW 0x7\r
+#define bRxSettle_LNA 0x38\r
+#define bRxSettle_RSSI 0x1c0\r
+#define bRxSettle_BBP 0xe00\r
+#define bRxSettle_RxHP 0x7000\r
+#define bRxSettle_AntSW_RSSI 0x38000\r
+#define bRxSettle_AntSW 0xc0000\r
+#define bRxProcessTime_DAGC 0x300000\r
+#define bRxSettle_HSSI 0x400000\r
+#define bRxProcessTime_BBPPW 0x800000\r
+#define bRxAntennaPowerShift 0x3000000\r
+#define bRSSITableSelect 0xc000000\r
+#define bRxHP_Final 0x7000000\r
+#define bRxHTSettle_BBP 0x7\r
+#define bRxHTSettle_HSSI 0x8\r
+#define bRxHTSettle_RxHP 0x70\r
+#define bRxHTSettle_BBPPW 0x80\r
+#define bRxHTSettle_Idle 0x300\r
+#define bRxHTSettle_Reserved 0x1c00\r
+#define bRxHTRxHPEn 0x8000\r
+#define bRxHTAGCFreezeThres 0x30000\r
+#define bRxHTAGCTogetherEn 0x40000\r
+#define bRxHTAGCMin 0x80000\r
+#define bRxHTAGCEn 0x100000\r
+#define bRxHTDAGCEn 0x200000\r
+#define bRxHTRxHP_BBP 0x1c00000\r
+#define bRxHTRxHP_Final 0xe0000000\r
+#define bRxPWRatioTH 0x3\r
+#define bRxPWRatioEn 0x4\r
+#define bRxMFHold 0x3800\r
+#define bRxPD_Delay_TH1 0x38\r
+#define bRxPD_Delay_TH2 0x1c0\r
+#define bRxPD_DC_COUNT_MAX 0x600\r
+//#define bRxMF_Hold 0x3800\r
+#define bRxPD_Delay_TH 0x8000\r
+#define bRxProcess_Delay 0xf0000\r
+#define bRxSearchrange_GI2_Early 0x700000\r
+#define bRxFrame_Guard_Counter_L 0x3800000\r
+#define bRxSGI_Guard_L 0xc000000\r
+#define bRxSGI_Search_L 0x30000000\r
+#define bRxSGI_TH 0xc0000000\r
+#define bDFSCnt0 0xff\r
+#define bDFSCnt1 0xff00\r
+#define bDFSFlag 0xf0000 \r
+#define bMFWeightSum 0x300000\r
+#define bMinIdxTH 0x7f000000 \r
+#define bDAFormat 0x40000 \r
+#define bTxChEmuEnable 0x01000000 \r
+#define bTRSWIsolation_A 0x7f\r
+#define bTRSWIsolation_B 0x7f00\r
+#define bTRSWIsolation_C 0x7f0000\r
+#define bTRSWIsolation_D 0x7f000000 \r
+#define bExtLNAGain 0x7c00 \r
+\r
+// 6. PageE(0xE00)\r
+#define bSTBCEn 0x4 // Useless\r
+#define bAntennaMapping 0x10\r
+#define bNss 0x20\r
+#define bCFOAntSumD 0x200\r
+#define bPHYCounterReset 0x8000000\r
+#define bCFOReportGet 0x4000000\r
+#define bOFDMContinueTx 0x10000000\r
+#define bOFDMSingleCarrier 0x20000000\r
+#define bOFDMSingleTone 0x40000000\r
+//#define bRxPath1 0x01\r
+//#define bRxPath2 0x02\r
+//#define bRxPath3 0x04\r
+//#define bRxPath4 0x08\r
+//#define bTxPath1 0x10\r
+//#define bTxPath2 0x20\r
+#define bHTDetect 0x100\r
+#define bCFOEn 0x10000\r
+#define bCFOValue 0xfff00000\r
+#define bSigTone_Re 0x3f\r
+#define bSigTone_Im 0x7f00\r
+#define bCounter_CCA 0xffff\r
+#define bCounter_ParityFail 0xffff0000\r
+#define bCounter_RateIllegal 0xffff\r
+#define bCounter_CRC8Fail 0xffff0000\r
+#define bCounter_MCSNoSupport 0xffff\r
+#define bCounter_FastSync 0xffff\r
+#define bShortCFO 0xfff\r
+#define bShortCFOTLength 12 //total\r
+#define bShortCFOFLength 11 //fraction\r
+#define bLongCFO 0x7ff\r
+#define bLongCFOTLength 11\r
+#define bLongCFOFLength 11\r
+#define bTailCFO 0x1fff\r
+#define bTailCFOTLength 13\r
+#define bTailCFOFLength 12 \r
+#define bmax_en_pwdB 0xffff\r
+#define bCC_power_dB 0xffff0000\r
+#define bnoise_pwdB 0xffff\r
+#define bPowerMeasTLength 10\r
+#define bPowerMeasFLength 3\r
+#define bRx_HT_BW 0x1\r
+#define bRxSC 0x6\r
+#define bRx_HT 0x8 \r
+#define bNB_intf_det_on 0x1\r
+#define bIntf_win_len_cfg 0x30\r
+#define bNB_Intf_TH_cfg 0x1c0 \r
+#define bRFGain 0x3f\r
+#define bTableSel 0x40\r
+#define bTRSW 0x80 \r
+#define bRxSNR_A 0xff\r
+#define bRxSNR_B 0xff00\r
+#define bRxSNR_C 0xff0000\r
+#define bRxSNR_D 0xff000000\r
+#define bSNREVMTLength 8\r
+#define bSNREVMFLength 1 \r
+#define bCSI1st 0xff\r
+#define bCSI2nd 0xff00\r
+#define bRxEVM1st 0xff0000\r
+#define bRxEVM2nd 0xff000000 \r
+#define bSIGEVM 0xff\r
+#define bPWDB 0xff00\r
+#define bSGIEN 0x10000\r
+ \r
+#define bSFactorQAM1 0xf // Useless\r
+#define bSFactorQAM2 0xf0\r
+#define bSFactorQAM3 0xf00\r
+#define bSFactorQAM4 0xf000\r
+#define bSFactorQAM5 0xf0000\r
+#define bSFactorQAM6 0xf0000\r
+#define bSFactorQAM7 0xf00000\r
+#define bSFactorQAM8 0xf000000\r
+#define bSFactorQAM9 0xf0000000\r
+#define bCSIScheme 0x100000\r
+ \r
+#define bNoiseLvlTopSet 0x3 // Useless\r
+#define bChSmooth 0x4\r
+#define bChSmoothCfg1 0x38\r
+#define bChSmoothCfg2 0x1c0\r
+#define bChSmoothCfg3 0xe00\r
+#define bChSmoothCfg4 0x7000\r
+#define bMRCMode 0x800000\r
+#define bTHEVMCfg 0x7000000\r
+ \r
+#define bLoopFitType 0x1 // Useless\r
+#define bUpdCFO 0x40\r
+#define bUpdCFOOffData 0x80\r
+#define bAdvUpdCFO 0x100\r
+#define bAdvTimeCtrl 0x800\r
+#define bUpdClko 0x1000\r
+#define bFC 0x6000\r
+#define bTrackingMode 0x8000\r
+#define bPhCmpEnable 0x10000\r
+#define bUpdClkoLTF 0x20000\r
+#define bComChCFO 0x40000\r
+#define bCSIEstiMode 0x80000\r
+#define bAdvUpdEqz 0x100000\r
+#define bUChCfg 0x7000000\r
+#define bUpdEqz 0x8000000\r
+\r
+//Rx Pseduo noise\r
+#define bRxPesudoNoiseOn 0x20000000 // Useless\r
+#define bRxPesudoNoise_A 0xff\r
+#define bRxPesudoNoise_B 0xff00\r
+#define bRxPesudoNoise_C 0xff0000\r
+#define bRxPesudoNoise_D 0xff000000\r
+#define bPesudoNoiseState_A 0xffff\r
+#define bPesudoNoiseState_B 0xffff0000\r
+#define bPesudoNoiseState_C 0xffff\r
+#define bPesudoNoiseState_D 0xffff0000\r
+\r
+//7. RF Register\r
+//Zebra1\r
+#define bZebra1_HSSIEnable 0x8 // Useless\r
+#define bZebra1_TRxControl 0xc00\r
+#define bZebra1_TRxGainSetting 0x07f\r
+#define bZebra1_RxCorner 0xc00\r
+#define bZebra1_TxChargePump 0x38\r
+#define bZebra1_RxChargePump 0x7\r
+#define bZebra1_ChannelNum 0xf80\r
+#define bZebra1_TxLPFBW 0x400\r
+#define bZebra1_RxLPFBW 0x600\r
+\r
+//Zebra4\r
+#define bRTL8256RegModeCtrl1 0x100 // Useless\r
+#define bRTL8256RegModeCtrl0 0x40\r
+#define bRTL8256_TxLPFBW 0x18\r
+#define bRTL8256_RxLPFBW 0x600\r
+\r
+//RTL8258\r
+#define bRTL8258_TxLPFBW 0xc // Useless\r
+#define bRTL8258_RxLPFBW 0xc00\r
+#define bRTL8258_RSSILPFBW 0xc0\r
+\r
+\r
+//\r
+// Other Definition\r
+//\r
+\r
+//byte endable for sb_write\r
+#define bByte0 0x1 // Useless\r
+#define bByte1 0x2\r
+#define bByte2 0x4\r
+#define bByte3 0x8\r
+#define bWord0 0x3\r
+#define bWord1 0xc\r
+#define bDWord 0xf\r
+\r
+//for PutRegsetting & GetRegSetting BitMask\r
+#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f\r
+#define bMaskByte1 0xff00\r
+#define bMaskByte2 0xff0000\r
+#define bMaskByte3 0xff000000\r
+#define bMaskHWord 0xffff0000\r
+#define bMaskLWord 0x0000ffff\r
+#define bMaskDWord 0xffffffff\r
+#define bMaskH3Bytes 0xffffff00\r
+#define bMask12Bits 0xfff \r
+#define bMaskH4Bits 0xf0000000 \r
+#define bMaskOFDM_D 0xffc00000\r
+#define bMaskCCK 0x3f3f3f3f\r
+\r
+//for PutRFRegsetting & GetRFRegSetting BitMask\r
+//#define bMask12Bits 0xfffff // RF Reg mask bits\r
+//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF\r
+#define bRFRegOffsetMask 0xfffff \r
+ \r
+#define bEnable 0x1 // Useless\r
+#define bDisable 0x0\r
+ \r
+#define LeftAntenna 0x0 // Useless\r
+#define RightAntenna 0x1\r
+ \r
+#define tCheckTxStatus 500 //500ms // Useless\r
+#define tUpdateRxCounter 100 //100ms\r
+ \r
+#define rateCCK 0 // Useless\r
+#define rateOFDM 1\r
+#define rateHT 2\r
+\r
+//define Register-End\r
+#define bPMAC_End 0x1ff // Useless\r
+#define bFPGAPHY0_End 0x8ff\r
+#define bFPGAPHY1_End 0x9ff\r
+#define bCCKPHY0_End 0xaff\r
+#define bOFDMPHY0_End 0xcff\r
+#define bOFDMPHY1_End 0xdff\r
+\r
+//define max debug item in each debug page\r
+//#define bMaxItem_FPGA_PHY0 0x9\r
+//#define bMaxItem_FPGA_PHY1 0x3\r
+//#define bMaxItem_PHY_11B 0x16\r
+//#define bMaxItem_OFDM_PHY0 0x29\r
+//#define bMaxItem_OFDM_PHY1 0x0\r
+\r
+#define bPMACControl 0x0 // Useless\r
+#define bWMACControl 0x1\r
+#define bWNICControl 0x2\r
+ \r
+#define PathA 0x0 // Useless\r
+#define PathB 0x1\r
+#define PathC 0x2\r
+#define PathD 0x3\r
+\r
+\r
+// RSSI Dump Message \r
+#define rA_RSSIDump_92E 0xcb0\r
+#define rB_RSSIDump_92E 0xcb1\r
+#define rS1_RXevmDump_92E 0xcb2 \r
+#define rS2_RXevmDump_92E 0xcb3\r
+#define rA_RXsnrDump_92E 0xcb4\r
+#define rB_RXsnrDump_92E 0xcb5\r
+#define rA_CfoShortDump_92E 0xcb6 \r
+#define rB_CfoShortDump_92E 0xcb8\r
+#define rA_CfoLongDump_92E 0xcba\r
+#define rB_CfoLongDump_92E 0xcbc\r
+\r
+/*--------------------------Define Parameters-------------------------------*/\r
+\r
+\r
+#endif //__INC_HAL8188EPHYREG_H\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff