--- /dev/null
+/*============================================================*/\r
+/* Description: */\r
+/* */\r
+/* This file is for 8814A TXBF mechanism */\r
+/* */\r
+/*============================================================*/\r
+\r
+#include "mp_precomp.h"\r
+#include "../phydm_precomp.h"\r
+\r
+#if (BEAMFORMING_SUPPORT == 1)\r
+#if (RTL8822B_SUPPORT == 1)\r
+\r
+#if 0\r
+VOID\r
+HalTxbf8814A_GetBeamformcap(\r
+ IN PADAPTER Adapter\r
+)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = GET_BEAMFORM_INFO(Adapter);\r
+ BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE;\r
+\r
+ BeamformCap = phydm_Beamforming_GetBeamCap(pDM_Odm, pBeamformingInfo);\r
+\r
+ if (BeamformCap == pBeamformingInfo->BeamformCap)\r
+ return;\r
+ else \r
+ pBeamformingInfo->BeamformCap = BeamformCap;\r
+\r
+}\r
+\r
+VOID\r
+HalTxbf8814A_GetTxRate(\r
+ IN PADAPTER Adapter\r
+)\r
+{\r
+\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;\r
+ PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter);\r
+ PRT_BEAMFORMEE_ENTRY pEntry;\r
+ u4Byte TxRptData = 0;\r
+ u1Byte DataRate = 0xFF;\r
+\r
+ pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]);\r
+\r
+ ReadSdramData_8814A(Adapter, (u1Byte)pEntry->MacId, LOC_8814A_CTRL_INFO, &TxRptData, 1);\r
+ DataRate = (u1Byte)TxRptData;\r
+ DataRate &= bMask7bits; /*Bit7 indicates SGI*/\r
+ \r
+ pDM_Odm->TxBfDataRate = DataRate;\r
+\r
+}\r
+\r
+VOID\r
+HalTxbf8814A_ResetTxPath(\r
+ IN PADAPTER Adapter,\r
+ IN u1Byte idx\r
+)\r
+{\r
+#if DEV_BUS_TYPE == RT_USB_INTERFACE\r
+\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); \r
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; \r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = GET_BEAMFORM_INFO(Adapter);\r
+ RT_BEAMFORMEE_ENTRY BeamformeeEntry;\r
+ u1Byte Nr_index = 0;\r
+ \r
+ if (idx < BEAMFORMEE_ENTRY_NUM)\r
+ BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx];\r
+ else\r
+ return;\r
+ \r
+ if ((pDM_Odm->LastUSBHub) != (RT_GetHubUSBMode(Adapter))) { \r
+ Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(Adapter), BeamformeeEntry.CompSteeringNumofBFer);\r
+\r
+ if (idx == 0) {\r
+ switch (Nr_index) { \r
+ case 0: \r
+ break;\r
+\r
+ case 1: /*Nsts = 2 BC*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT3|BIT2|BIT1|BIT0, 0x6); /*1ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT7|BIT6|BIT5|BIT4, 0x6); /*2ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0x0000ff00, 0x10); /*BC*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0x6); /*set TxPath selection for 8814a BFer bug refine*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x10); /*if Bfer enable, always use 3Tx for all Spatial stream*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x1060);\r
+ break;\r
+\r
+ case 2: /*Nsts = 3 BCD*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT3|BIT2|BIT1|BIT0, 0xe); /*1ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT7|BIT6|BIT5|BIT4, 0xe); /*2ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0x0000ff00, 0x90); /*BCD*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT19|BIT18|BIT17|BIT16, 0xe); /*3ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0xff00000, 0x90); /*bcd*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0xe); /*set TxPath selection for 8814a BFer bug refine*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x90); /*if Bfer enable, always use 3Tx for all Spatial stream*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x90e90e0);\r
+ break;\r
+ \r
+ default: /*Nr>3, same as Case 3*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT3|BIT2|BIT1|BIT0, 0xf); /*1ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT7|BIT6|BIT5|BIT4, 0xf); /*2ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0x0000ff00, 0x93); /*BC*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT19|BIT18|BIT17|BIT16, 0xf); /*3ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0xff00000, 0x93); /*bcd*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0xf); /*set TxPath selection for 8814a BFer bug refine*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x93); /*if Bfer enable, always use 3Tx for all Spatial stream*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93f93f0);\r
+ break;\r
+ }\r
+ } else {\r
+ switch (Nr_index) {\r
+ case 0: \r
+ break;\r
+\r
+ case 1: /*Nsts = 2 BC*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT3|BIT2|BIT1|BIT0, 0x6); /*1ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT7|BIT6|BIT5|BIT4, 0x6); /*2ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0x0000ff00, 0x10); /*BC*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0x6); /*set TxPath selection for 8814a BFer bug refine*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x10); /*if Bfer enable, always use 3Tx for all Spatial stream*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x1060);\r
+ break;\r
+\r
+ case 2: /*Nsts = 3 BCD*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT3|BIT2|BIT1|BIT0, 0xe); /*1ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT7|BIT6|BIT5|BIT4, 0xe); /*2ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0x0000ff00, 0x90); /*BC*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT19|BIT18|BIT17|BIT16, 0xe); /*3ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0xff00000, 0x90); /*bcd*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0xe); /*set TxPath selection for 8814a BFer bug refine*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x90); /*if Bfer enable, always use 3Tx for all Spatial stream*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x90e90e0);\r
+ break;\r
+ \r
+ default: /*Nr>3, same as Case 3*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT3|BIT2|BIT1|BIT0, 0xf); /*1ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT7|BIT6|BIT5|BIT4, 0xf); /*2ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0x0000ff00, 0x93); /*BC*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT19|BIT18|BIT17|BIT16, 0xf); /*3ss*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0xff00000, 0x93); /*bcd*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0xf); /*set TxPath selection for 8814a BFer bug refine*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x93); /*if Bfer enable, always use 3Tx for all Spatial stream*/\r
+ PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93f93f0);\r
+ break;\r
+ \r
+ }\r
+ }\r
+\r
+ pDM_Odm->LastUSBHub = RT_GetHubUSBMode(Adapter);\r
+ }\r
+ else\r
+ return;\r
+#endif\r
+}\r
+#endif\r
+\r
+u1Byte\r
+halTxbf8822B_GetNtx(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte Ntx = 0;\r
+\r
+#if DEV_BUS_TYPE == RT_USB_INTERFACE\r
+ if (pDM_Odm->SupportInterface == ODM_ITRF_USB) {\r
+ if (*pDM_Odm->HubUsbMode == 2) {/*USB3.0*/\r
+ if (pDM_Odm->RFType == ODM_4T4R)\r
+ Ntx = 3;\r
+ else if (pDM_Odm->RFType == ODM_3T3R)\r
+ Ntx = 2;\r
+ else\r
+ Ntx = 1;\r
+ } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/\r
+ Ntx = 1;\r
+ else\r
+ Ntx = 1;\r
+ } else\r
+#endif\r
+ {\r
+ if (pDM_Odm->RFType == ODM_4T4R)\r
+ Ntx = 3;\r
+ else if (pDM_Odm->RFType == ODM_3T3R)\r
+ Ntx = 2;\r
+ else\r
+ Ntx = 1;\r
+ }\r
+\r
+ return Ntx;\r
+\r
+}\r
+\r
+u1Byte\r
+halTxbf8822B_GetNrx(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte Nrx = 0;\r
+\r
+ if (pDM_Odm->RFType == ODM_4T4R)\r
+ Nrx = 3;\r
+ else if (pDM_Odm->RFType == ODM_3T3R)\r
+ Nrx = 2;\r
+ else if (pDM_Odm->RFType == ODM_2T2R)\r
+ Nrx = 1;\r
+ else if (pDM_Odm->RFType == ODM_2T3R)\r
+ Nrx = 2;\r
+ else if (pDM_Odm->RFType == ODM_2T4R)\r
+ Nrx = 3;\r
+ else if (pDM_Odm->RFType == ODM_1T1R)\r
+ Nrx = 0;\r
+ else if (pDM_Odm->RFType == ODM_1T2R)\r
+ Nrx = 1;\r
+ else\r
+ Nrx = 0;\r
+\r
+ return Nrx;\r
+ \r
+}\r
+\r
+/***************SU & MU BFee Entry********************/\r
+VOID\r
+halTxbf8822B_RfMode(\r
+ IN PVOID pDM_VOID,\r
+ IN PRT_BEAMFORMING_INFO pBeamformingInfo,\r
+ IN u1Byte idx\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte i, Nr_index = 0;\r
+ BOOLEAN bSelfBeamformer = FALSE;\r
+ BOOLEAN bSelfBeamformee = FALSE;\r
+ RT_BEAMFORMEE_ENTRY BeamformeeEntry;\r
+\r
+ if (idx < BEAMFORMEE_ENTRY_NUM)\r
+ BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx];\r
+ else\r
+ return;\r
+\r
+ if (pDM_Odm->RFType == ODM_1T1R)\r
+ return;\r
+\r
+ for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) {\r
+ ODM_SetRFReg(pDM_Odm, i, RF_WeLut_Jaguar, 0x80000, 0x1);\r
+ /*RF Mode table write enable*/\r
+ }\r
+\r
+ if ((pBeamformingInfo->beamformee_su_cnt > 0) || (pBeamformingInfo->beamformee_mu_cnt > 0)) {\r
+ for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) {\r
+ ODM_SetRFReg(pDM_Odm, i, RF_ModeTableAddr, 0xfffff, 0x18000);\r
+ /*Select RX mode*/\r
+ ODM_SetRFReg(pDM_Odm, i, RF_ModeTableData0, 0xfffff, 0xBE77F);\r
+ /*Set Table data*/\r
+ ODM_SetRFReg(pDM_Odm, i, RF_ModeTableData1, 0xfffff, 0x226BF);\r
+ /*Enable TXIQGEN in RX mode*/\r
+ }\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF);\r
+ /*Enable TXIQGEN in RX mode*/\r
+ }\r
+\r
+ for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) {\r
+ ODM_SetRFReg(pDM_Odm, i, RF_WeLut_Jaguar, 0x80000, 0x0);\r
+ /*RF Mode table write disable*/\r
+ }\r
+\r
+ if (pBeamformingInfo->beamformee_su_cnt > 0) {\r
+\r
+ /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, BIT28|BIT29, 0x2); /*enable BB TxBF ant mapping register*/\r
+ \r
+ if (idx == 0) {\r
+ /*Nsts = 2 AB*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0, 0xffff, 0x0433);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, 0xfff00000, 0x043);\r
+ /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430);*/\r
+\r
+ } else {/*IDX =1*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, 0xffff, 0x0433);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, 0xfff00000, 0x043);\r
+ /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430;*/\r
+ }\r
+ } else {\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, 0xfff00000, 0x1); /*1SS by path-A*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430); /*2SS by path-A,B*/\r
+ }\r
+ \r
+ if (pBeamformingInfo->beamformee_mu_cnt > 0) {\r
+ /*MU STAs share the common setting*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, BIT31, 1);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, 0xffff, 0x0433);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, 0xfff00000, 0x043);\r
+ }\r
+\r
+}\r
+#if 0\r
+VOID\r
+halTxbf8822B_DownloadNDPA(\r
+ IN PADAPTER Adapter,\r
+ IN u1Byte Idx\r
+ )\r
+{\r
+ u1Byte u1bTmp = 0, tmpReg422 = 0;\r
+ u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0;\r
+ u2Byte Head_Page = 0x7FE;\r
+ BOOLEAN bSendBeacon = FALSE;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/\r
+ PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter);\r
+ PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx;\r
+\r
+ pHalData->bFwDwRsvdPageInProgress = TRUE;\r
+ Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy);\r
+ \r
+ /*Set REG_CR bit 8. DMA beacon by SW.*/\r
+ u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1);\r
+ PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp|BIT0));\r
+\r
+\r
+ /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/\r
+ tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2);\r
+ PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422&(~BIT6));\r
+\r
+ if (tmpReg422 & BIT6) {\r
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an Adapter is sending beacon.\n"));\r
+ bSendBeacon = TRUE;\r
+ }\r
+\r
+ /*0x204[11:0] Beacon Head for TXDMA*/\r
+ PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, Head_Page);\r
+ \r
+ do { \r
+ /*Clear beacon valid check bit.*/\r
+ BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1);\r
+ PlatformEFIOWrite1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1, (BcnValidReg|BIT7));\r
+ \r
+ /*download NDPA rsvd page.*/\r
+ if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)\r
+ Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE);\r
+ else \r
+ Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);\r
+ \r
+ /*check rsvd page download OK.*/\r
+ BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);\r
+ count = 0;\r
+ while (!(BcnValidReg & BIT7) && count < 20) {\r
+ count++;\r
+ delay_us(10);\r
+ BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+2);\r
+ }\r
+ DLBcnCount++;\r
+ } while (!(BcnValidReg & BIT7) && DLBcnCount < 5);\r
+ \r
+ if (!(BcnValidReg & BIT0))\r
+ RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__));\r
+\r
+ /*0x204[11:0] Beacon Head for TXDMA*/\r
+ PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy);\r
+\r
+ /*To make sure that if there exists an adapter which would like to send beacon.*/\r
+ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/\r
+ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */\r
+ /*the beacon cannot be sent by HW.*/\r
+ /*2010.06.23. Added by tynli.*/\r
+ if (bSendBeacon)\r
+ PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422);\r
+\r
+ /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/\r
+ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/\r
+ u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1);\r
+ PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp&(~BIT0)));\r
+\r
+ pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;\r
+\r
+ pHalData->bFwDwRsvdPageInProgress = FALSE;\r
+}\r
+\r
+VOID\r
+halTxbf8822B_FwTxBFCmd(\r
+ IN PADAPTER Adapter\r
+ )\r
+{\r
+ u1Byte Idx, Period = 0;\r
+ u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF;\r
+ u1Byte u1TxBFParm[3] = {0};\r
+\r
+ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);\r
+ PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter);\r
+\r
+ for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {\r
+ if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\r
+ if (pBeamInfo->BeamformeeEntry[Idx].bSound) {\r
+ PageNum0 = 0xFE;\r
+ PageNum1 = 0x07;\r
+ Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);\r
+ } else if (PageNum0 == 0xFF) {\r
+ PageNum0 = 0xFF; /*stop sounding*/\r
+ PageNum1 = 0x0F;\r
+ }\r
+ }\r
+ }\r
+\r
+ u1TxBFParm[0] = PageNum0;\r
+ u1TxBFParm[1] = PageNum1;\r
+ u1TxBFParm[2] = Period;\r
+ FillH2CCmd(Adapter, PHYDM_H2C_TXBF, 3, u1TxBFParm);\r
+ \r
+ RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x Period = %d", __func__, PageNum0, PageNum1, Period));\r
+}\r
+#endif\r
+\r
+VOID\r
+HalTxbf8822B_Init(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte u1bTmp;\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+\r
+ ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT16, 1); /*Enable P1 aggr new packet according to P0 transfer time*/\r
+ ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT15|BIT14|BIT13|BIT12, 1); /*MU Retry Limit*/\r
+ ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT7, 0); /*Disable Tx MU-MIMO until sounding done*/ \r
+ ODM_SetBBReg(pDM_Odm, 0x14c0 , 0x3F, 0); /* Clear validity of MU STAs */\r
+ ODM_Write1Byte(pDM_Odm, 0x167c , 0x70); /*MU-MIMO Option as default value*/\r
+ ODM_Write2Byte(pDM_Odm, 0x1680 , 0); /*MU-MIMO Control as default value*/\r
+\r
+ /* Set MU NDPA rate & BW source */\r
+ /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, 0x42C);\r
+ ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B, (u1bTmp|BIT6));\r
+ /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */\r
+ ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, 0x10);\r
+\r
+ /* Init HW variable */\r
+ pBeamformingInfo->RegMUTxCtrl = ODM_Read4Byte(pDM_Odm, 0x14c0);\r
+}\r
+\r
+VOID\r
+HalTxbf8822B_Enter(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte BFerBFeeIdx\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte i = 0;\r
+ u1Byte BFerIdx = (BFerBFeeIdx & 0xF0)>>4;\r
+ u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);\r
+ u2Byte CSI_Param = 0;\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+ PRT_BEAMFORMEE_ENTRY pBeamformeeEntry;\r
+ PRT_BEAMFORMER_ENTRY pBeamformerEntry;\r
+ u2Byte value16, STAid = 0;\r
+ u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;\r
+ u4Byte gid_valid, user_position_l, user_position_h;\r
+ u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};\r
+ u1Byte u1bTmp;\r
+ u4Byte u4bTmp;\r
+ \r
+ RT_DISP(FBEAM, FBEAM_FUN, ("%s: BFerBFeeIdx=%d, BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerBFeeIdx, BFerIdx, BFeeIdx));\r
+\r
+ /*************SU BFer Entry Init*************/\r
+ if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {\r
+ pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx];\r
+ pBeamformerEntry->is_mu_ap = FALSE;\r
+ /*Sounding protocol control*/\r
+ ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); \r
+ \r
+ \r
+ for (i = 0; i < MAX_BEAMFORMER_SU; i++) {\r
+ if ((pBeamformingInfo->beamformer_su_reg_maping & BIT(i)) == 0) {\r
+ pBeamformingInfo->beamformer_su_reg_maping |= BIT(i);\r
+ pBeamformerEntry->su_reg_index = i;\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /*MAC address/Partial AID of Beamformer*/\r
+ if (pBeamformerEntry->su_reg_index == 0) {\r
+ for (i = 0; i < 6 ; i++)\r
+ ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]);\r
+ } else {\r
+ for (i = 0; i < 6 ; i++)\r
+ ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8822B+i), pBeamformerEntry->MacAddr[i]);\r
+ }\r
+\r
+ /*CSI report parameters of Beamformer*/\r
+ Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/\r
+ Nr_index = pBeamformerEntry->NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/\r
+ \r
+ grouping = 0;\r
+\r
+ /*for ac = 1, for n = 3*/\r
+ if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU)\r
+ codebookinfo = 1; \r
+ else if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT)\r
+ codebookinfo = 3; \r
+\r
+ coefficientsize = 3;\r
+\r
+ CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index));\r
+\r
+ if (BFerIdx == 0)\r
+ ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8822B, CSI_Param);\r
+ else\r
+ ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8822B+2, CSI_Param);\r
+ /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/\r
+ ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A+3, 0x70);\r
+ \r
+ }\r
+\r
+ /*************SU BFee Entry Init*************/\r
+ if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {\r
+ pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx];\r
+ pBeamformeeEntry->is_mu_sta = FALSE;\r
+ halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx);\r
+ \r
+ if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))\r
+ STAid = pBeamformeeEntry->MacId;\r
+ else \r
+ STAid = pBeamformeeEntry->P_AID;\r
+\r
+ for (i = 0; i < MAX_BEAMFORMEE_SU; i++) {\r
+ if ((pBeamformingInfo->beamformee_su_reg_maping & BIT(i)) == 0) {\r
+ pBeamformingInfo->beamformee_su_reg_maping |= BIT(i);\r
+ pBeamformeeEntry->su_reg_index = i;\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/\r
+ if (pBeamformeeEntry->su_reg_index == 0) { \r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, STAid); \r
+ ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7);\r
+ } else {\r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, STAid | BIT14 | BIT15 | BIT12);\r
+ } \r
+\r
+ /*CSI report parameters of Beamformee*/\r
+ if (pBeamformeeEntry->su_reg_index == 0) {\r
+ /*Get BIT24 & BIT25*/\r
+ u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+3) & 0x3;\r
+ \r
+ ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60);\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, STAid | BIT9);\r
+ } else \r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, STAid | 0xE200); /*Set BIT25*/\r
+ \r
+ phydm_Beamforming_Notify(pDM_Odm);\r
+ }\r
+\r
+ /*************MU BFer Entry Init*************/\r
+ if ((pBeamformingInfo->beamformer_mu_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {\r
+ pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx];\r
+ pBeamformingInfo->mu_ap_index = BFerIdx;\r
+ pBeamformerEntry->is_mu_ap = TRUE;\r
+ for (i = 0; i < 8; i++)\r
+ pBeamformerEntry->gid_valid[i] = 0;\r
+ for (i = 0; i < 16; i++)\r
+ pBeamformerEntry->user_position[i] = 0;\r
+ \r
+ /*Sounding protocol control*/\r
+ ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); \r
+ \r
+ /* MAC address */\r
+ for (i = 0; i < 6 ; i++)\r
+ ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]);\r
+\r
+ /* Set partial AID */\r
+ ODM_Write2Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+6), pBeamformerEntry->P_AID);\r
+\r
+ /* Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, 0x1680);\r
+ u1bTmp = (pBeamformerEntry->AID)&0xFFF;\r
+ ODM_Write1Byte(pDM_Odm, 0x1680, u1bTmp);\r
+\r
+ /* Set 80us for leaving ndp_rx_standby_state */\r
+ ODM_Write1Byte(pDM_Odm, 0x71B, 0x50);\r
+ \r
+ /* Set 0x6A0[14] = 1 to accept action_no_ack */\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1);\r
+ u1bTmp |= 0x40;\r
+ ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp);\r
+ /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP1_8822B);\r
+ u1bTmp |= 0x30;\r
+ ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP1_8822B, u1bTmp);\r
+ \r
+ /*CSI report parameters of Beamformer*/\r
+ Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /* Depend on RF type */\r
+ Nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/\r
+ grouping = 0; /*no grouping*/\r
+ codebookinfo = 1; /*7 bit for psi, 9 bit for phi*/\r
+ coefficientsize = 0; /*This is nothing really matter*/ \r
+ CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index));\r
+ ODM_Write2Byte(pDM_Odm, 0x6F4, CSI_Param);\r
+\r
+ }\r
+ \r\r
+ /*************MU BFee Entry Init*************/\r
+ if ((pBeamformingInfo->beamformee_mu_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {\r
+ pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx];\r
+ pBeamformeeEntry->is_mu_sta = TRUE;\r
+ for (i = 0; i < MAX_BEAMFORMEE_MU; i++) {\r
+ if ((pBeamformingInfo->beamformee_mu_reg_maping & BIT(i)) == 0) {\r
+ pBeamformingInfo->beamformee_mu_reg_maping |= BIT(i);\r
+ pBeamformeeEntry->mu_reg_index = i;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (pBeamformeeEntry->mu_reg_index == 0xFF) {\r
+ /* There is no valid bit in beamformee_mu_reg_maping */\r
+ RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__));\r
+ return;\r
+ }\r
+ \r
+ /*User position table*/\r
+ switch (pBeamformeeEntry->mu_reg_index) {\r
+ case 0:\r
+ gid_valid = 0x7fe;\r
+ user_position_l = 0x111110;\r
+ user_position_h = 0x0;\r
+ break;\r
+ case 1:\r
+ gid_valid = 0x7f806;\r
+ user_position_l = 0x11000004;\r
+ user_position_h = 0x11;\r
+ break;\r
+ case 2:\r
+ gid_valid = 0x1f81818;\r
+ user_position_l = 0x400040;\r
+ user_position_h = 0x11100;\r
+ break;\r
+ case 3:\r
+ gid_valid = 0x1e186060;\r
+ user_position_l = 0x4000400;\r
+ user_position_h = 0x1100040;\r
+ break;\r
+ case 4:\r
+ gid_valid = 0x66618180;\r
+ user_position_l = 0x40004000;\r
+ user_position_h = 0x10040400;\r
+ break;\r
+ case 5:\r
+ gid_valid = 0x79860600;\r
+ user_position_l = 0x40000;\r
+ user_position_h = 0x4404004;\r
+ break;\r
+ }\r
+\r
+ for (i = 0; i < 8; i++) {\r
+ if (i < 4) {\r
+ pBeamformeeEntry->gid_valid[i] = (u1Byte)(gid_valid & 0xFF);\r
+ gid_valid = (gid_valid >> 8);\r
+ } else\r
+ pBeamformeeEntry->gid_valid[i] = 0;\r
+ }\r
+ for (i = 0; i < 16; i++) {\r
+ if (i < 4) {\r
+ pBeamformeeEntry->user_position[i] = (u1Byte)(user_position_l & 0xFF);\r
+ user_position_l = user_position_l >> 8;\r
+ } else if (i < 8) {\r
+ pBeamformeeEntry->user_position[i] = (u1Byte)(user_position_h & 0xFF);\r
+ user_position_h = user_position_h >> 8;\r
+ } else\r
+ pBeamformeeEntry->user_position[i] = 0;\r
+ }\r
+\r
+ /*Sounding protocol control*/\r
+ ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); \r
+\r
+ /*select MU STA table*/\r
+ pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10);\r
+ pBeamformingInfo->RegMUTxCtrl |= (pBeamformeeEntry->mu_reg_index << 8)&(BIT8|BIT9|BIT10);\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); \r
+ \r
+ ODM_SetBBReg(pDM_Odm, 0x14c4 , bMaskDWord, 0); /*Reset gid_valid table*/\r
+ ODM_SetBBReg(pDM_Odm, 0x14c8 , bMaskDWord, user_position_l);\r
+ ODM_SetBBReg(pDM_Odm, 0x14cc , bMaskDWord, user_position_h);\r
+\r
+ /*set validity of MU STAs*/ \r
+ pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0;\r
+ pBeamformingInfo->RegMUTxCtrl |= pBeamformingInfo->beamformee_mu_reg_maping&0x3F;\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); \r
+\r
+ value16 = ODM_Read2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index]);\r
+ value16 &= 0xFE00; /*Clear PAID*/\r
+ value16 |= BIT9; /*Enable MU BFee*/\r
+ value16 |= pBeamformeeEntry->P_AID;\r
+ ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , value16);\r
+ \r
+ /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3);\r
+ u1bTmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/\r
+ ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, u1bTmp);\r
+ /* Set NDPA to 6M*/\r
+ ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8822B, 0x4); /* 6M */\r
+\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B);\r
+ u1bTmp &= 0xFC; /* Clear bit 0, 1*/\r
+ ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, u1bTmp);\r
+\r
+ u4bTmp = ODM_Read4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B);\r
+ u4bTmp = ((u4bTmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202 */\r
+ ODM_Write4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, u4bTmp); \r
+\r
+ /* Set 0x6A0[14] = 1 to accept action_no_ack */\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1);\r
+ u1bTmp |= 0x40;\r
+ ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp);\r
+ /* End of MAC registers setting */\r
+ \r
+ halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx);\r
+#if (SUPPORT_MU_BF == 1)\r
+ /*Special for plugfest*/\r
+ delay_ms(50); /* wait for 4-way handshake ending*/\r
+ SendSWVHTGIDMgntFrame(pDM_Odm, pBeamformeeEntry->MacAddr, BFeeIdx);\r
+#endif \r
+\r
+ phydm_Beamforming_Notify(pDM_Odm);\r
+\r
+ }\r
+\r
+}\r
+\r
+\r
+VOID\r
+HalTxbf8822B_Leave(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Idx\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+ PRT_BEAMFORMER_ENTRY pBeamformerEntry; \r
+ PRT_BEAMFORMEE_ENTRY pBeamformeeEntry;\r
+ u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};\r
+\r
+ if (Idx < BEAMFORMER_ENTRY_NUM) {\r
+ pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[Idx];\r
+ pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[Idx];\r
+ } else\r
+ return;\r
+\r
+ /*Clear P_AID of Beamformee*/\r
+ /*Clear MAC address of Beamformer*/\r
+ /*Clear Associated Bfmee Sel*/\r
+\r
+ if (pBeamformerEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) {\r
+ ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xD8); \r
+ if (pBeamformerEntry->is_mu_ap == 0) { /*SU BFer */\r
+ if (pBeamformerEntry->su_reg_index == 0) { \r
+ ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0);\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0);\r
+ ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8822B, 0);\r
+ } else {\r
+ ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0);\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0);\r
+ ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8822B+2, 0);\r
+ }\r
+ pBeamformingInfo->beamformer_su_reg_maping &= ~(BIT(pBeamformerEntry->su_reg_index));\r
+ pBeamformerEntry->su_reg_index = 0xFF;\r
+ } else { /*MU BFer */\r
+ /*set validity of MU STA0 and MU STA1*/\r
+ pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0;\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl);\r
+ \r
+ ODM_Memory_Set(pDM_Odm, pBeamformerEntry->gid_valid, 0, 8);\r
+ ODM_Memory_Set(pDM_Odm, pBeamformerEntry->user_position, 0, 16);\r
+ pBeamformerEntry->is_mu_ap = FALSE;\r
+ }\r
+ }\r
+\r
+ if (pBeamformeeEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) {\r
+ halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, Idx);\r
+ if (pBeamformeeEntry->is_mu_sta == 0) { /*SU BFee*/\r
+ if (pBeamformeeEntry->su_reg_index == 0) { \r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, 0x0); \r
+ ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7);\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0);\r
+ } else {\r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, 0x0 | BIT14 | BIT15 | BIT12);\r
+\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, \r
+ ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2) & 0x60);\r
+ }\r
+ pBeamformingInfo->beamformee_su_reg_maping &= ~(BIT(pBeamformeeEntry->su_reg_index));\r
+ pBeamformeeEntry->su_reg_index = 0xFF;\r
+ } else { /*MU BFee */\r
+ /*Disable sending NDPA & BF-rpt-poll to this BFee*/\r
+ ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , 0);\r
+ /*set validity of MU STA*/\r
+ pBeamformingInfo->RegMUTxCtrl &= ~(BIT(pBeamformeeEntry->mu_reg_index));\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl);\r
+ \r
+ \r
+ pBeamformeeEntry->is_mu_sta = FALSE;\r
+ pBeamformingInfo->beamformee_mu_reg_maping &= ~(BIT(pBeamformeeEntry->mu_reg_index));\r
+ pBeamformeeEntry->mu_reg_index = 0xFF;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/***********SU & MU BFee Entry Only when souding done****************/\r
+VOID\r
+HalTxbf8822B_Status(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Idx\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u2Byte BeamCtrlVal, tmpVal;\r
+ u4Byte BeamCtrlReg;\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+ PRT_BEAMFORMEE_ENTRY pBeamformEntry;\r
+ BOOLEAN is_mu_sounding = pBeamformingInfo->is_mu_sounding, is_bitmap_ready = FALSE;\r
+ u16 bitmap;\r
+ u8 idx, gid, i;\r
+ u8 id1, id0;\r
+ u32 gid_valid[6] = {0};\r
+ u32 user_position_lsb[6] = {0};\r
+ u32 user_position_msb[6] = {0};\r
+ u32 value32;\r
+\r
+ if (Idx < BEAMFORMEE_ENTRY_NUM)\r
+ pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[Idx];\r
+ else\r
+ return;\r
+ \r
+ /*SU sounding done */\r
+ if (is_mu_sounding == FALSE) {\r
+\r
+ if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))\r
+ BeamCtrlVal = pBeamformEntry->MacId;\r
+ else \r
+ BeamCtrlVal = pBeamformEntry->P_AID;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, pBeamformEntry->BeamformEntryState));\r
+\r
+ if (pBeamformEntry->su_reg_index == 0) {\r
+ BeamCtrlReg = REG_TXBF_CTRL_8822B;\r
+ } else {\r
+ BeamCtrlReg = REG_TXBF_CTRL_8822B+2;\r
+ BeamCtrlVal |= BIT12|BIT14|BIT15;\r
+ }\r
+\r
+ if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\r
+ if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_20)\r
+ BeamCtrlVal |= BIT9;\r
+ else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_40)\r
+ BeamCtrlVal |= (BIT9|BIT10);\r
+ else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_80)\r
+ BeamCtrlVal |= (BIT9|BIT10|BIT11); \r
+ } else {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__));\r
+ BeamCtrlVal &= ~(BIT9|BIT10|BIT11);\r
+ }\r
+\r
+ ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);\r
+ /*disable NDP packet use beamforming */\r
+ tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8822B);\r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, tmpVal|BIT15);\r
+ } else {\r
+ /*MU sounding done */\r
+ if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\r
+ /*value32 = ODM_GetBBReg(pDM_Odm, 0xF4C, 0xFFFF0000);*/\r
+ value32 = 1;\r
+ \r
+ is_bitmap_ready = (BOOLEAN)((value32 & BIT15) >> 15);\r
+ bitmap = (u16)(value32 & 0x3FFF);\r
+ \r
+ for (idx = 0; idx < 15; idx++) {\r
+ if (idx < 5) {/*bit0~4*/\r
+ id0 = 0;\r
+ id1 = (u8)(idx + 1);\r
+ } else if (idx < 9) { /*bit5~8*/\r
+ id0 = 1;\r
+ id1 = (u8)(idx - 3);\r
+ } else if (idx < 12) { /*bit9~11*/\r
+ id0 = 2;\r
+ id1 = (u8)(idx - 6);\r
+ } else if (idx < 14) { /*bit12~13*/ \r
+ id0 = 3;\r
+ id1 = (u8)(idx - 8);\r
+ } else { /*bit14*/\r
+ id0 = 4;\r
+ id1 = (u8)(idx - 9);\r
+ }\r
+ if (bitmap & BIT(idx)) {\r
+ /*Pair 1*/\r
+ gid = (idx << 1) + 1;\r
+ gid_valid[id0] |= (BIT(gid));\r
+ gid_valid[id1] |= (BIT(gid));\r
+ /*Pair 2*/\r
+ gid += 1;\r
+ gid_valid[id0] |= (BIT(gid));\r
+ gid_valid[id1] |= (BIT(gid));\r
+ } else {\r
+ /*Pair 1*/\r
+ gid = (idx << 1) + 1;\r
+ gid_valid[id0] &= ~(BIT(gid));\r
+ gid_valid[id1] &= ~(BIT(gid));\r
+ /*Pair 2*/\r
+ gid += 1;\r
+ gid_valid[id0] &= ~(BIT(gid));\r
+ gid_valid[id1] &= ~(BIT(gid));\r
+ }\r
+ }\r
+\r
+ for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\r
+ pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[i];\r
+ if ((pBeamformEntry->is_mu_sta) && (pBeamformEntry->mu_reg_index < 6)) {\r
+ value32 = gid_valid[pBeamformEntry->mu_reg_index];\r
+ for (idx = 0; idx < 4; idx++) {\r
+ pBeamformEntry->gid_valid[idx] = (u8)(value32 & 0xFF);\r
+ value32 = (value32 >> 8);\r
+ }\r
+ }\r
+ }\r
+\r
+ for (idx = 0; idx < 6; idx++) {\r
+ pBeamformingInfo->RegMUTxCtrl |= ~(BIT8|BIT9|BIT10);\r
+ pBeamformingInfo->RegMUTxCtrl |= ((idx<<8)&(BIT8|BIT9|BIT10));\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl);\r
+ ODM_SetMACReg(pDM_Odm, 0x14C4, bMaskDWord, gid_valid[idx]); /*set MU STA gid valid table*/\r
+ }\r
+\r
+ /*Enable TxMU PPDU*/\r
+ pBeamformingInfo->RegMUTxCtrl |= BIT7;\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl);\r
+ }\r
+ }\r
+}\r
+\r
+/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/\r
+VOID\r
+HalTxbf8822B_ConfigGtab(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+ PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL;\r
+ u4Byte gid_valid = 0, user_position_l = 0, user_position_h = 0, i;\r
+\r
+ if (pBeamformingInfo->mu_ap_index < BEAMFORMER_ENTRY_NUM)\r
+ pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[pBeamformingInfo->mu_ap_index];\r
+ else\r
+ return;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s==>\n", __func__));\r
+\r
+ /*For GID 0~31*/\r
+ for (i = 0; i < 4; i++)\r
+ gid_valid |= (pBeamformerEntry->gid_valid[i] << (i<<3));\r
+ for (i = 0; i < 8; i++) {\r
+ if (i < 4)\r
+ user_position_l |= (pBeamformerEntry->user_position[i] << (i << 3));\r
+ else\r
+ user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 4)<<3));\r
+ }\r
+ /*select MU STA0 table*/\r
+ pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10);\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl);\r
+ ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); \r
+ ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l);\r
+ ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h);\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",\r
+ __func__, gid_valid, user_position_l, user_position_h));\r
+\r
+ gid_valid = 0;\r
+ user_position_l = 0;\r
+ user_position_h = 0;\r
+\r
+ /*For GID 32~64*/\r
+ for (i = 4; i < 8; i++)\r
+ gid_valid |= (pBeamformerEntry->gid_valid[i] << ((i - 4)<<3));\r
+ for (i = 8; i < 16; i++) {\r
+ if (i < 4)\r
+ user_position_l |= (pBeamformerEntry->user_position[i] << ((i - 8) << 3));\r
+ else\r
+ user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 12) << 3));\r
+ }\r
+ /*select MU STA1 table*/\r
+ pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10);\r
+ pBeamformingInfo->RegMUTxCtrl |= BIT8;\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl);\r
+ ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); \r
+ ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l);\r
+ ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h);\r
+ \r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",\r
+ __func__, gid_valid, user_position_l, user_position_h));\r
+\r
+ /* Set validity of MU STA0 and MU STA1*/\r
+ pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0;\r
+ pBeamformingInfo->RegMUTxCtrl |= 0x3; /* STA0, STA1*/\r
+ ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl);\r
+ \r
+}\r
+\r
+\r
+\r
+#if 0\r
+/*This function translate the bitmap to GTAB*/\r
+VOID\r
+haltxbf8822b_gtab_translation(\r
+ IN PDM_ODM_T pDM_Odm\r
+) \r
+{\r
+ u8 idx, gid;\r
+ u8 id1, id0;\r
+ u32 gid_valid[6] = {0};\r
+ u32 user_position_lsb[6] = {0};\r
+ u32 user_position_msb[6] = {0};\r
+ \r
+ for (idx = 0; idx < 15; idx++) {\r
+ if (idx < 5) {/*bit0~4*/\r
+ id0 = 0;\r
+ id1 = (u8)(idx + 1);\r
+ } else if (idx < 9) { /*bit5~8*/\r
+ id0 = 1;\r
+ id1 = (u8)(idx - 3);\r
+ } else if (idx < 12) { /*bit9~11*/\r
+ id0 = 2;\r
+ id1 = (u8)(idx - 6);\r
+ } else if (idx < 14) { /*bit12~13*/ \r
+ id0 = 3;\r
+ id1 = (u8)(idx - 8);\r
+ } else { /*bit14*/\r
+ id0 = 4;\r
+ id1 = (u8)(idx - 9);\r
+ }\r
+\r
+ /*Pair 1*/\r
+ gid = (idx << 1) + 1;\r
+ gid_valid[id0] |= (1 << gid);\r
+ gid_valid[id1] |= (1 << gid);\r
+ if (gid < 16) {\r
+ /*user_position_lsb[id0] |= (0 << (gid << 1));*/\r
+ user_position_lsb[id1] |= (1 << (gid << 1));\r
+ } else {\r
+ /*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/\r
+ user_position_msb[id1] |= (1 << ((gid - 16) << 1));\r
+ }\r
+ \r
+ /*Pair 2*/\r
+ gid += 1;\r
+ gid_valid[id0] |= (1 << gid);\r
+ gid_valid[id1] |= (1 << gid);\r
+ if (gid < 16) {\r
+ user_position_lsb[id0] |= (1 << (gid << 1));\r
+ /*user_position_lsb[id1] |= (0 << (gid << 1));*/\r
+ } else {\r
+ user_position_msb[id0] |= (1 << ((gid - 16) << 1));\r
+ /*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/\r
+ }\r
+\r
+ }\r
+\r
+\r
+ for (idx = 0; idx < 6; idx++) {\r
+ /*DbgPrint("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]);\r
+ DbgPrint("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/\r
+ }\r
+}\r
+#endif\r
+\r
+VOID\r
+HalTxbf8822B_FwTxBF(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Idx\r
+ )\r
+{\r
+#if 0\r
+ PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter);\r
+ PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx;\r
+\r
+ if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)\r
+ halTxbf8822B_DownloadNDPA(Adapter, Idx);\r
+\r
+ halTxbf8822B_FwTxBFCmd(Adapter);\r
+#endif\r
+}\r
+\r
+#else /* (RTL8822B_SUPPORT == 1)*/\r
+\r
+#endif /* (RTL8822B_SUPPORT == 1)*/\r
+\r
+#endif /*(BEAMFORMING_SUPPORT == 1)*/\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff