--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ * \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+//============================================================\r
+// include files\r
+//============================================================\r
+#include "mp_precomp.h"\r
+#include "phydm_precomp.h"\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+\r
+#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD\r
+#define MODE_40M 0 //0:20M, 1:40M\r
+#define PSD_TH2 3 \r
+#define PSD_CHMIN 20 // Minimum channel number for BT AFH\r
+#define SIR_STEP_SIZE 3\r
+#define Smooth_Size_1 5\r
+#define Smooth_TH_1 3\r
+#define Smooth_Size_2 10\r
+#define Smooth_TH_2 4\r
+#define Smooth_Size_3 20\r
+#define Smooth_TH_3 4\r
+#define Smooth_Step_Size 5\r
+#define Adaptive_SIR 1\r
+#define SCAN_INTERVAL 1500 //ms\r
+#define SYN_Length 5 // for 92D\r
+ \r
+#define LNA_Low_Gain_1 0x64\r
+#define LNA_Low_Gain_2 0x5A\r
+#define LNA_Low_Gain_3 0x58\r
+\r
+#define pw_th_10dB 0x0\r
+#define pw_th_16dB 0x3\r
+\r
+#define FA_RXHP_TH1 5000\r
+#define FA_RXHP_TH2 1500\r
+#define FA_RXHP_TH3 800\r
+#define FA_RXHP_TH4 600\r
+#define FA_RXHP_TH5 500\r
+\r
+#define Idle_Mode 0\r
+#define High_TP_Mode 1\r
+#define Low_TP_Mode 2\r
+\r
+\r
+VOID\r
+odm_PSDMonitorInit(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ //PSD Monitor Setting\r
+ //Which path in ADC/DAC is turnned on for PSD: both I/Q\r
+ ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3);\r
+ //Ageraged number: 8\r
+ ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1);\r
+ pDM_Odm->bPSDinProcess = FALSE;\r
+ pDM_Odm->bUserAssignLevel = FALSE;\r
+ pDM_Odm->bPSDactive = FALSE;\r
+ //pDM_Odm->bDMInitialGainEnable=TRUE; //change the initialization to DIGinit\r
+ //Set Debug Port\r
+ //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803);\r
+ //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD\r
+ //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan\r
+ //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval\r
+\r
+ //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms\r
+#endif\r
+}\r
+\r
+VOID\r
+PatchDCTone(\r
+ IN PVOID pDM_VOID,\r
+ pu4Byte PSD_report,\r
+ u1Byte initial_gain_psd\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ //PADAPTER pAdapter;\r
+ \r
+ u4Byte psd_report;\r
+\r
+ //2 Switch to CH11 to patch CH9 and CH13 DC tone\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 11);\r
+ \r
+ if(pDM_Odm->SupportICType== ODM_RTL8192D)\r
+ {\r
+ if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))\r
+ {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 11);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x77C1A);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x41289);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01840);\r
+ }\r
+ else\r
+ {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x77C1A);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x41289);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01840);\r
+ }\r
+ }\r
+ \r
+ //Ch9 DC tone patch\r
+ psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);\r
+ PSD_report[50] = psd_report;\r
+ //Ch13 DC tone patch\r
+ psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);\r
+ PSD_report[70] = psd_report;\r
+ \r
+ //2 Switch to CH3 to patch CH1 and CH5 DC tone\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 3);\r
+\r
+ \r
+ if(pDM_Odm->SupportICType==ODM_RTL8192D)\r
+ {\r
+ if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))\r
+ {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 3);\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x07C1A);\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x61289);\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01C41);\r
+ }\r
+ else\r
+ {\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x07C1A);\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x61289);\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01C41);\r
+ }\r
+ }\r
+ \r
+ //Ch1 DC tone patch\r
+ psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);\r
+ PSD_report[10] = psd_report;\r
+ //Ch5 DC tone patch\r
+ psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);\r
+ PSD_report[30] = psd_report;\r
+\r
+}\r
+\r
+\r
+VOID\r
+GoodChannelDecision(\r
+ IN PVOID pDM_VOID,\r
+ pu4Byte PSD_report,\r
+ pu1Byte PSD_bitmap,\r
+ u1Byte RSSI_BT,\r
+ pu1Byte PSD_bitmap_memory)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;\r
+ //s4Byte TH1 = SSBT-0x15; // modify TH by Neil Chen\r
+ s4Byte TH1= RSSI_BT+0x14;\r
+ s4Byte TH2 = RSSI_BT+85;\r
+ //u2Byte TH3;\r
+// s4Byte RegB34;\r
+ u1Byte bitmap, Smooth_size[3], Smooth_TH[3];\r
+ //u1Byte psd_bit;\r
+ u4Byte i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3];\r
+ int start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ;\r
+ \r
+// RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF;\r
+\r
+ if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D))\r
+ {\r
+ TH1 = RSSI_BT + 0x14; \r
+ }\r
+\r
+ Smooth_size[0]=Smooth_Size_1;\r
+ Smooth_size[1]=Smooth_Size_2;\r
+ Smooth_size[2]=Smooth_Size_3;\r
+ Smooth_TH[0]=Smooth_TH_1;\r
+ Smooth_TH[1]=Smooth_TH_2;\r
+ Smooth_TH[2]=Smooth_TH_3;\r
+ Smooth_Interval[0]=16;\r
+ Smooth_Interval[1]=15;\r
+ Smooth_Interval[2]=13;\r
+ good_cnt = 0;\r
+ if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
+ {\r
+ //2 Threshold \r
+\r
+ if(RSSI_BT >=41)\r
+ TH1 = 113; \r
+ else if(RSSI_BT >=38) // >= -15dBm\r
+ TH1 = 105; //0x69\r
+ else if((RSSI_BT >=33)&(RSSI_BT <38))\r
+ TH1 = 99+(RSSI_BT-33); //0x63\r
+ else if((RSSI_BT >=26)&(RSSI_BT<33))\r
+ TH1 = 99-(33-RSSI_BT)+2; //0x5e\r
+ else if((RSSI_BT >=24)&(RSSI_BT<26))\r
+ TH1 = 88-((RSSI_BT-24)*3); //0x58\r
+ else if((RSSI_BT >=18)&(RSSI_BT<24))\r
+ TH1 = 77+((RSSI_BT-18)*2);\r
+ else if((RSSI_BT >=14)&(RSSI_BT<18))\r
+ TH1 = 63+((RSSI_BT-14)*2);\r
+ else if((RSSI_BT >=8)&(RSSI_BT<14))\r
+ TH1 = 58+((RSSI_BT-8)*2);\r
+ else if((RSSI_BT >=3)&(RSSI_BT<8))\r
+ TH1 = 52+(RSSI_BT-3);\r
+ else\r
+ TH1 = 51;\r
+ }\r
+\r
+ for (i = 0; i< 10; i++)\r
+ PSD_bitmap[i] = 0;\r
+ \r
+\r
+ // Add By Gary\r
+ for (i=0; i<80; i++)\r
+ pRX_HP_Table->PSD_bitmap_RXHP[i] = 0;\r
+ // End\r
+\r
+\r
+\r
+ if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
+ {\r
+ TH1 =TH1-SIR_STEP_SIZE;\r
+ }\r
+ while (good_cnt < PSD_CHMIN)\r
+ {\r
+ good_cnt = 0;\r
+ if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
+ {\r
+ if(TH1 ==TH2)\r
+ break;\r
+ if((TH1+SIR_STEP_SIZE) < TH2)\r
+ TH1 += SIR_STEP_SIZE;\r
+ else\r
+ TH1 = TH2;\r
+ }\r
+ else\r
+ {\r
+ if(TH1==(RSSI_BT+0x1E))\r
+ break; \r
+ if((TH1+2) < (RSSI_BT+0x1E))\r
+ TH1+=3;\r
+ else\r
+ TH1 = RSSI_BT+0x1E; \r
+ \r
+ }\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1));\r
+ \r
+ for (i = 0; i< 80; i++)\r
+ {\r
+ if((s4Byte)(PSD_report[i]) < TH1)\r
+ {\r
+ byte_idx = i / 8;\r
+ bit_idx = i -8*byte_idx;\r
+ bitmap = PSD_bitmap[byte_idx];\r
+ PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx);\r
+ }\r
+ }\r
+\r
+#if DBG\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: before smoothing\n"));\r
+ for(n=0;n<10;n++)\r
+ {\r
+ //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]);\r
+ for (i = 0; i<8; i++)\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] = %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));\r
+ }\r
+#endif\r
+ \r
+ //1 Start of smoothing function\r
+\r
+ for (j=0;j<3;j++)\r
+ {\r
+ start_byte_idx=0;\r
+ start_bit_idx=0;\r
+ for(n=0; n<Smooth_Interval[j]; n++)\r
+ {\r
+ good_cnt_smoothing = 0;\r
+ cur_bit_idx = start_bit_idx;\r
+ cur_byte_idx = start_byte_idx;\r
+ for ( i=0; i < Smooth_size[j]; i++)\r
+ {\r
+ NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;\r
+ if ( (PSD_bitmap[NOW_byte_idx]& BIT( (cur_bit_idx + i)%8)) != 0)\r
+ good_cnt_smoothing++;\r
+\r
+ }\r
+\r
+ if( good_cnt_smoothing < Smooth_TH[j] )\r
+ {\r
+ cur_bit_idx = start_bit_idx;\r
+ cur_byte_idx = start_byte_idx;\r
+ for ( i=0; i< Smooth_size[j] ; i++)\r
+ { \r
+ NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8; \r
+ PSD_bitmap[NOW_byte_idx] = PSD_bitmap[NOW_byte_idx] & (~BIT( (cur_bit_idx + i)%8));\r
+ }\r
+ }\r
+ start_bit_idx = start_bit_idx + Smooth_Step_Size;\r
+ while ( (start_bit_idx) > 7 )\r
+ {\r
+ start_byte_idx= start_byte_idx+start_bit_idx/8;\r
+ start_bit_idx = start_bit_idx%8;\r
+ }\r
+ }\r
+\r
+ ODM_RT_TRACE( pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1));\r
+ for(n=0;n<10;n++)\r
+ {\r
+ for (i = 0; i<8; i++)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] = %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));\r
+ \r
+ if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1) //----- Add By Gary\r
+ {\r
+ pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1;\r
+ } // ------end by Gary\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ \r
+ good_cnt = 0;\r
+ for ( i = 0; i < 10; i++)\r
+ {\r
+ for (n = 0; n < 8; n++)\r
+ if((PSD_bitmap[i]& BIT(n)) != 0)\r
+ good_cnt++;\r
+ }\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, ODM_COMP_PSD,("PSD: good channel cnt = %u",good_cnt));\r
+ }\r
+\r
+ //RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1));\r
+ for (i = 0; i <10; i++)\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i]));\r
+/* \r
+ //Update bitmap memory\r
+ for(i = 0; i < 80; i++)\r
+ {\r
+ byte_idx = i / 8;\r
+ bit_idx = i -8*byte_idx;\r
+ psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx;\r
+ bitmap = PSD_bitmap_memory[i]; \r
+ PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit;\r
+ }\r
+*/\r
+}\r
+\r
+\r
+\r
+VOID\r
+odm_PSD_Monitor(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ //PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;\r
+\r
+ unsigned int pts, start_point, stop_point;\r
+ u1Byte initial_gain ;\r
+ static u1Byte PSD_bitmap_memory[80], init_memory = 0;\r
+ static u1Byte psd_cnt=0;\r
+ static u4Byte PSD_report[80], PSD_report_tmp;\r
+ static u8Byte lastTxOkCnt=0, lastRxOkCnt=0;\r
+ u1Byte H2C_PSD_DATA[5]={0,0,0,0,0};\r
+ static u1Byte H2C_PSD_DATA_last[5] ={0,0,0,0,0};\r
+ u1Byte idx[20]={96,99,102,106,109,112,115,118,122,125,\r
+ 0,3,6,10,13,16,19,22,26,29};\r
+ u1Byte n, i, channel, BBReset,tone_idx;\r
+ u1Byte PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;\r
+ s4Byte PSD_skip_start, PSD_skip_stop;\r
+ u4Byte CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;\r
+ u4Byte ReScan, Interval, Is40MHz;\r
+ u8Byte curTxOkCnt, curRxOkCnt;\r
+ int cur_byte_idx, cur_bit_idx;\r
+ PADAPTER Adapter = pDM_Odm->Adapter;\r
+ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;\r
+ \r
+\r
+ if(*pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("pbDriverIsGoingToPnpSetPowerSleep!!!!!!!!!!!!!!!\n"));\r
+ return;\r
+ }\r
+\r
+ \r
+ if( (*(pDM_Odm->pbScanInProcess)) ||\r
+ pDM_Odm->bLinkInProcess)\r
+ {\r
+ if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))\r
+ {\r
+ ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 1500); //ms \r
+ //psd_cnt=0;\r
+ }\r
+ return;\r
+ }\r
+\r
+ if(pDM_Odm->bBtHsOperation)\r
+ {\r
+ ReScan = 1;\r
+ Interval = SCAN_INTERVAL;\r
+ }\r
+ else\r
+ {\r
+ ReScan = PSD_RESCAN;\r
+ Interval = SCAN_INTERVAL;\r
+ }\r
+\r
+ //1 Initialization\r
+ if(init_memory == 0)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Init memory\n"));\r
+ for(i = 0; i < 80; i++)\r
+ PSD_bitmap_memory[i] = 0xFF; // channel is always good\r
+ init_memory = 1;\r
+ }\r
+ if(psd_cnt == 0)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));\r
+ for(i = 0; i < 80; i++)\r
+ PSD_report[i] = 0;\r
+ }\r
+\r
+ //1 Backup Current Settings\r
+ CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);\r
+/*\r
+ if(pDM_Odm->SupportICType==ODM_RTL8192D)\r
+ {\r
+ //2 Record Current synthesizer parameters based on current channel\r
+ if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY))\r
+ {\r
+ SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x25, bMaskDWord);\r
+ SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x26, bMaskDWord);\r
+ SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x27, bMaskDWord);\r
+ SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, bMaskDWord);\r
+ SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, bMaskDWord);\r
+ }\r
+ else // DualMAC_DualPHY 2G\r
+ {\r
+ SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x25, bMaskDWord);\r
+ SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x26, bMaskDWord);\r
+ SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x27, bMaskDWord);\r
+ SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, bMaskDWord);\r
+ SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, bMaskDWord);\r
+ }\r
+ }\r
+*/\r
+ //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);\r
+ RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);\r
+\r
+ //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28;\r
+ RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;\r
+\r
+ //2???\r
+ if(CHNL_RUN_ABOVE_40MHZ(pMgntInfo))\r
+ Is40MHz = TRUE;\r
+ else\r
+ Is40MHz = FALSE;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));\r
+ //1 Turn off CCK\r
+ //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0);\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);\r
+ //1 Turn off TX\r
+ //Pause TX Queue\r
+ //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF);\r
+ ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF);\r
+ \r
+ //Force RX to stop TX immediately\r
+ //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);\r
+\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);\r
+ //1 Turn off RX\r
+ //Rx AGC off RegC70[0]=0, RegC7C[20]=0\r
+ //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0);\r
+ //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0);\r
+\r
+ ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);\r
+ ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);\r
+\r
+ \r
+ //Turn off CCA\r
+ //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0);\r
+ ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);\r
+ \r
+ //BB Reset\r
+ //BBReset = PlatformEFIORead1Byte(Adapter, 0x02);\r
+ BBReset = ODM_Read1Byte(pDM_Odm, 0x02);\r
+ \r
+ //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0));\r
+ //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0);\r
+ ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess \r
+ ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));\r
+ ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);\r
+ ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);\r
+ \r
+ //1 Leave RX idle low power\r
+ //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0);\r
+\r
+ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);\r
+ //1 Fix initial gain\r
+ //if (IS_HARDWARE_TYPE_8723AE(Adapter))\r
+ //RSSI_BT = pHalData->RSSI_BT;\r
+ //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter))) // Add by Gary\r
+ // RSSI_BT = RSSI_BT_new;\r
+\r
+ if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))\r
+ RSSI_BT=pDM_Odm->RSSI_BT; //need to check C2H to pDM_Odm RSSI BT\r
+\r
+ if(RSSI_BT>=47)\r
+ RSSI_BT=47;\r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));\r
+ \r
+ if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
+ {\r
+ //Neil add--2011--10--12\r
+ //2 Initial Gain index \r
+ if(RSSI_BT >=35) // >= -15dBm\r
+ initial_gain_psd = RSSI_BT*2;\r
+ else if((RSSI_BT >=33)&(RSSI_BT<35))\r
+ initial_gain_psd = RSSI_BT*2+6;\r
+ else if((RSSI_BT >=24)&(RSSI_BT<33))\r
+ initial_gain_psd = 70-(33-RSSI_BT);\r
+ else if((RSSI_BT >=19)&(RSSI_BT<24))\r
+ initial_gain_psd = 64-((24-RSSI_BT)*4);\r
+ else if((RSSI_BT >=14)&(RSSI_BT<19))\r
+ initial_gain_psd = 44-((18-RSSI_BT)*2);\r
+ else if((RSSI_BT >=8)&(RSSI_BT<14))\r
+ initial_gain_psd = 35-(14-RSSI_BT);\r
+ else\r
+ initial_gain_psd = 0x1B;\r
+ }\r
+ else\r
+ {\r
+ \r
+ //need to do \r
+ initial_gain_psd = pDM_Odm->RSSI_Min; // PSD report based on RSSI\r
+ //} \r
+ }\r
+ //if(RSSI_BT<0x17)\r
+ // RSSI_BT +=3;\r
+ //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT);\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));\r
+\r
+ //initialGainUpper = 0x5E; //Modify by neil chen\r
+ \r
+ if(pDM_Odm->bUserAssignLevel)\r
+ {\r
+ pDM_Odm->bUserAssignLevel = FALSE;\r
+ initialGainUpper = 0x7f;\r
+ }\r
+ else\r
+ {\r
+ initialGainUpper = 0x5E;\r
+ }\r
+ \r
+ /*\r
+ if (initial_gain_psd < 0x1a)\r
+ initial_gain_psd = 0x1a;\r
+ if (initial_gain_psd > initialGainUpper)\r
+ initial_gain_psd = initialGainUpper;\r
+ */\r
+\r
+ //if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
+ SSBT = RSSI_BT * 2 +0x3E;\r
+ \r
+ \r
+ //if(IS_HARDWARE_TYPE_8723AE(Adapter))\r
+ // SSBT = RSSI_BT * 2 +0x3E;\r
+ //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter))) // Add by Gary\r
+ //{\r
+ // RSSI_BT = initial_gain_psd;\r
+ // SSBT = RSSI_BT;\r
+ //}\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));\r
+ ODM_RT_TRACE( pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));\r
+ //DbgPrint("PSD: SSBT= %d", SSBT);\r
+ //need to do\r
+ pDM_Odm->bDMInitialGainEnable = FALSE;\r
+ initial_gain =(u1Byte) (ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F);\r
+ \r
+ // make sure the initial gain is under the correct range.\r
+ //initial_gain_psd &= 0x7f;\r
+ ODM_Write_DIG(pDM_Odm, initial_gain_psd);\r
+ //1 Turn off 3-wire\r
+ ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);\r
+\r
+ //pts value = 128, 256, 512, 1024\r
+ pts = 128;\r
+\r
+ if(pts == 128)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);\r
+ start_point = 64;\r
+ stop_point = 192;\r
+ }\r
+ else if(pts == 256)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);\r
+ start_point = 128;\r
+ stop_point = 384;\r
+ }\r
+ else if(pts == 512)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);\r
+ start_point = 256;\r
+ stop_point = 768;\r
+ }\r
+ else\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);\r
+ start_point = 512;\r
+ stop_point = 1536;\r
+ }\r
+ \r
+\r
+//3 Skip WLAN channels if WLAN busy\r
+\r
+ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;\r
+ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;\r
+ lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);\r
+ lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); \r
+\r
+ PSD_skip_start=80;\r
+ PSD_skip_stop = 0;\r
+ wlan_channel = CurrentChannel & 0x0f;\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));\r
+ if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
+ {\r
+ if(pDM_Odm->bBtHsOperation)\r
+ {\r
+ if(pDM_Odm->bLinked)\r
+ {\r
+ if(Is40MHz)\r
+ {\r
+ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask\r
+ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;\r
+ }\r
+ else\r
+ {\r
+ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10; // Modify by Neil to add 10 chs to mask\r
+ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ // mask for 40MHz\r
+ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask\r
+ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;\r
+ }\r
+ if(PSD_skip_start < 0)\r
+ PSD_skip_start = 0;\r
+ if(PSD_skip_stop >80)\r
+ PSD_skip_stop = 80;\r
+ }\r
+ else\r
+ {\r
+ if((curRxOkCnt+curTxOkCnt) > 5)\r
+ {\r
+ if(Is40MHz)\r
+ {\r
+ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask\r
+ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;\r
+ }\r
+ else\r
+ {\r
+ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10; // Modify by Neil to add 10 chs to mask\r
+ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; \r
+ }\r
+ \r
+ if(PSD_skip_start < 0)\r
+ PSD_skip_start = 0;\r
+ if(PSD_skip_stop >80)\r
+ PSD_skip_stop = 80;\r
+ }\r
+ }\r
+ }\r
+#if 0 \r
+ else\r
+ {\r
+ if((curRxOkCnt+curTxOkCnt) > 1000)\r
+ {\r
+ PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;\r
+ PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;\r
+ }\r
+ } \r
+#endif //Reove RXHP Issue\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));\r
+\r
+ for (n=0;n<80;n++)\r
+ {\r
+ if((n%20)==0)\r
+ {\r
+ channel = (n/20)*4 + 1;\r
+ \r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);\r
+ }\r
+ tone_idx = n%20;\r
+ if ((n>=PSD_skip_start) && (n<PSD_skip_stop))\r
+ { \r
+ PSD_report[n] = SSBT;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));\r
+ }\r
+ else\r
+ {\r
+ PSD_report_tmp = GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);\r
+\r
+ if ( PSD_report_tmp > PSD_report[n])\r
+ PSD_report[n] = PSD_report_tmp;\r
+ \r
+ }\r
+ }\r
+\r
+ PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);\r
+ \r
+ //----end\r
+ //1 Turn on RX\r
+ //Rx AGC on\r
+ ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);\r
+ ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);\r
+ //CCK on\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);\r
+ //1 Turn on TX\r
+ //Resume TX Queue\r
+ \r
+ ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00);\r
+ //Turn on 3-wire\r
+ ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);\r
+ //1 Restore Current Settings\r
+ //Resume DIG\r
+ pDM_Odm->bDMInitialGainEnable = TRUE;\r
+ \r
+ ODM_Write_DIG(pDM_Odm, initial_gain);\r
+\r
+ // restore originl center frequency\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);\r
+\r
+ //Turn on CCA\r
+ ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);\r
+ //Restore RX idle low power\r
+ if(RxIdleLowPwr == TRUE)\r
+ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);\r
+ \r
+ psd_cnt++;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));\r
+ if (psd_cnt < ReScan)\r
+ ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval); \r
+ else\r
+ {\r
+ psd_cnt = 0;\r
+ for(i=0;i<80;i++)\r
+ //DbgPrint("psd_report[%d]= %d \n", 2402+i, PSD_report[i]);\r
+ RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("psd_report[%d]= %d \n", 2402+i, PSD_report[i]));\r
+\r
+\r
+ GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);\r
+\r
+ if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
+ {\r
+ cur_byte_idx=0;\r
+ cur_bit_idx=0;\r
+\r
+ //2 Restore H2C PSD Data to Last Data\r
+ H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0];\r
+ H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1];\r
+ H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2];\r
+ H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3];\r
+ H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4];\r
+\r
+ \r
+ //2 Translate 80bit channel map to 40bit channel \r
+ for ( i=0;i<5;i++)\r
+ {\r
+ for(n=0;n<8;n++)\r
+ {\r
+ cur_byte_idx = i*2 + n/4;\r
+ cur_bit_idx = (n%4)*2;\r
+ if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0))\r
+ H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n);\r
+ }\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i]));\r
+ }\r
+ \r
+ //3 To Compare the difference\r
+ for ( i=0;i<5;i++)\r
+ {\r
+ if(H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i])\r
+ {\r
+ FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA);\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("Need to Update the AFH Map \n"));\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ if(i==5)\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Not need to Update\n")); \r
+ }\r
+ }\r
+ if(pDM_Odm->bBtHsOperation)\r
+ {\r
+ ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 10000);\r
+ ODM_RT_TRACE( pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n")); \r
+ }\r
+ else\r
+ {\r
+ ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 1500);\r
+ ODM_RT_TRACE( pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n")); \r
+ }\r
+ }\r
+ }\r
+}\r
+/*\r
+//Neil for Get BT RSSI\r
+// Be Triggered by BT C2H CMD\r
+VOID\r
+ODM_PSDGetRSSI(\r
+ IN u1Byte RSSI_BT)\r
+{\r
+\r
+\r
+}\r
+\r
+*/\r
+\r
+VOID\r
+ODM_PSDMonitor(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ \r
+ //if(IS_HARDWARE_TYPE_8723AE(Adapter))\r
+ \r
+ if(pDM_Odm->SupportICType == ODM_RTL8723A) //may need to add other IC type\r
+ {\r
+ if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)\r
+ {\r
+ if(!pDM_Odm->bBtEnabled) //need to check upper layer connection\r
+ {\r
+ pDM_Odm->bPSDactive=FALSE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n"));\r
+ return; \r
+ }\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n"));\r
+ //{\r
+ pDM_Odm->bPSDinProcess = TRUE;\r
+ pDM_Odm->bPSDactive=TRUE;\r
+ odm_PSD_Monitor(pDM_Odm);\r
+ pDM_Odm->bPSDinProcess = FALSE;\r
+ } \r
+ } \r
+\r
+}\r
+VOID\r
+odm_PSDMonitorCallback(\r
+ PRT_TIMER pTimer\r
+)\r
+{\r
+ PADAPTER Adapter = (PADAPTER)pTimer->Adapter;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+\r
+ PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem);\r
+}\r
+\r
+VOID\r
+odm_PSDMonitorWorkItemCallback(\r
+ IN PVOID pContext\r
+ )\r
+{\r
+ PADAPTER Adapter = (PADAPTER)pContext;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;\r
+\r
+ ODM_PSDMonitor(pDM_Odm);\r
+}\r
+\r
+\r
+ //cosa debug tool need to modify\r
+\r
+VOID\r
+ODM_PSDDbgControl(\r
+ IN PADAPTER Adapter,\r
+ IN u4Byte mode,\r
+ IN u4Byte btRssi\r
+ )\r
+{\r
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi));\r
+ if(mode)\r
+ {\r
+ pDM_Odm->RSSI_BT = (u1Byte)btRssi;\r
+ pDM_Odm->bUserAssignLevel = TRUE;\r
+ ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms \r
+ }\r
+ else\r
+ {\r
+ ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);\r
+ }\r
+#endif\r
+}\r
+\r
+\r
+//#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+\r
+void odm_RXHPInit(\r
+ IN PVOID pDM_VOID)\r
+{\r
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;\r
+ u1Byte index;\r
+\r
+ pRX_HP_Table->RXHP_enable = TRUE;\r
+ pRX_HP_Table->RXHP_flag = 0;\r
+ pRX_HP_Table->PSD_func_trigger = 0;\r
+ pRX_HP_Table->Pre_IGI = 0x20;\r
+ pRX_HP_Table->Cur_IGI = 0x20;\r
+ pRX_HP_Table->Cur_pw_th = pw_th_10dB;\r
+ pRX_HP_Table->Pre_pw_th = pw_th_10dB;\r
+ for(index=0; index<80; index++)\r
+ pRX_HP_Table->PSD_bitmap_RXHP[index] = 1;\r
+\r
+#if(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+ pRX_HP_Table->TP_Mode = Idle_Mode;\r
+#endif\r
+#endif\r
+}\r
+\r
+VOID\r
+odm_PSD_RXHP(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;\r
+ PADAPTER Adapter = pDM_Odm->Adapter;\r
+ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);\r
+ unsigned int pts, start_point, stop_point, initial_gain ;\r
+ static u1Byte PSD_bitmap_memory[80], init_memory = 0;\r
+ static u1Byte psd_cnt=0;\r
+ static u4Byte PSD_report[80], PSD_report_tmp;\r
+ static u8Byte lastTxOkCnt=0, lastRxOkCnt=0;\r
+ u1Byte idx[20]={96,99,102,106,109,112,115,118,122,125,\r
+ 0,3,6,10,13,16,19,22,26,29};\r
+ u1Byte n, i, channel, BBReset,tone_idx;\r
+ u1Byte PSD_bitmap[10]/*, SSBT=0*/,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;\r
+ s4Byte PSD_skip_start, PSD_skip_stop;\r
+ u4Byte CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;\r
+ u4Byte ReScan, Interval, Is40MHz;\r
+ u8Byte curTxOkCnt, curRxOkCnt;\r
+ //--------------2G band synthesizer for 92D switch RF channel using----------------- \r
+ u1Byte group_idx=0;\r
+ u4Byte SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0;\r
+ u4Byte SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C}; // synthesizer RF register for 2G channel\r
+ u4Byte SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, // For CH1,2,4,9,10.11.12 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}\r
+ {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, // For CH3,13,14\r
+ {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}}; // For Ch5,6,7,8\r
+ //--------------------- Add by Gary for Debug setting ----------------------\r
+ u1Byte RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF);\r
+ u1Byte rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF);\r
+ //---------------------------------------------------------------------\r
+ \r
+ if(pMgntInfo->bScanInProgress)\r
+ {\r
+ return;\r
+ }\r
+\r
+ ReScan = PSD_RESCAN;\r
+ Interval = SCAN_INTERVAL;\r
+\r
+\r
+ //1 Initialization\r
+ if(init_memory == 0)\r
+ {\r
+ RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("Init memory\n"));\r
+ for(i = 0; i < 80; i++)\r
+ PSD_bitmap_memory[i] = 0xFF; // channel is always good\r
+ init_memory = 1;\r
+ }\r
+ if(psd_cnt == 0)\r
+ {\r
+ RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));\r
+ for(i = 0; i < 80; i++)\r
+ PSD_report[i] = 0;\r
+ }\r
+\r
+ //1 Backup Current Settings\r
+ CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);\r
+ if(pDM_Odm->SupportICType == ODM_RTL8192D)\r
+ {\r
+ //2 Record Current synthesizer parameters based on current channel\r
+ if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))\r
+ {\r
+ SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord);\r
+ SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord);\r
+ SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord);\r
+ SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord);\r
+ SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord);\r
+ }\r
+ else // DualMAC_DualPHY 2G\r
+ {\r
+ SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord);\r
+ SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord);\r
+ SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord);\r
+ SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord);\r
+ SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord);\r
+ }\r
+ }\r
+ RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);\r
+ RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;\r
+ Is40MHz = *(pDM_Odm->pBandWidth);\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));\r
+ //1 Turn off CCK\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);\r
+ //1 Turn off TX\r
+ //Pause TX Queue\r
+ ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);\r
+ //Force RX to stop TX immediately\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);\r
+ //1 Turn off RX\r
+ //Rx AGC off RegC70[0]=0, RegC7C[20]=0\r
+ ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);\r
+ ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);\r
+ //Turn off CCA\r
+ ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);\r
+ //BB Reset\r
+ ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess \r
+ BBReset = ODM_Read1Byte(pDM_Odm, 0x02);\r
+ ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));\r
+ ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);\r
+ ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);\r
+ //1 Leave RX idle low power\r
+ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);\r
+ //1 Fix initial gain\r
+ RSSI_BT = RSSI_BT_new;\r
+ RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));\r
+ \r
+ if(rssi_ctrl == 1) // just for debug!!\r
+ initial_gain_psd = RSSI_BT_new; \r
+ else\r
+ initial_gain_psd = pDM_Odm->RSSI_Min; // PSD report based on RSSI\r
+ \r
+ RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));\r
+ \r
+ initialGainUpper = 0x54;\r
+ \r
+ RSSI_BT = initial_gain_psd;\r
+ //SSBT = RSSI_BT;\r
+ \r
+ //RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));\r
+ RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));\r
+ \r
+ pDM_Odm->bDMInitialGainEnable = FALSE; \r
+ initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F;\r
+ //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd); \r
+ ODM_Write_DIG(pDM_Odm, initial_gain_psd);\r
+ //1 Turn off 3-wire\r
+ ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);\r
+\r
+ //pts value = 128, 256, 512, 1024\r
+ pts = 128;\r
+\r
+ if(pts == 128)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);\r
+ start_point = 64;\r
+ stop_point = 192;\r
+ }\r
+ else if(pts == 256)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);\r
+ start_point = 128;\r
+ stop_point = 384;\r
+ }\r
+ else if(pts == 512)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);\r
+ start_point = 256;\r
+ stop_point = 768;\r
+ }\r
+ else\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);\r
+ start_point = 512;\r
+ stop_point = 1536;\r
+ }\r
+ \r
+\r
+//3 Skip WLAN channels if WLAN busy\r
+ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;\r
+ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;\r
+ lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);\r
+ lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);\r
+ \r
+ PSD_skip_start=80;\r
+ PSD_skip_stop = 0;\r
+ wlan_channel = CurrentChannel & 0x0f;\r
+\r
+ RT_TRACE(ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));\r
+ \r
+ if((curRxOkCnt+curTxOkCnt) > 1000)\r
+ {\r
+ PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;\r
+ PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;\r
+ }\r
+\r
+ RT_TRACE(ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));\r
+\r
+ for (n=0;n<80;n++)\r
+ {\r
+ if((n%20)==0)\r
+ {\r
+ channel = (n/20)*4 + 1;\r
+ if(pDM_Odm->SupportICType == ODM_RTL8192D)\r
+ {\r
+ switch(channel)\r
+ {\r
+ case 1: \r
+ case 9:\r
+ group_idx = 0;\r
+ break;\r
+ case 5:\r
+ group_idx = 2;\r
+ break;\r
+ case 13:\r
+ group_idx = 1;\r
+ break;\r
+ }\r
+ if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) \r
+ {\r
+ for(i = 0; i < SYN_Length; i++)\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]);\r
+\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, channel);\r
+ }\r
+ else // DualMAC_DualPHY 2G\r
+ {\r
+ for(i = 0; i < SYN_Length; i++)\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]); \r
+ \r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);\r
+ }\r
+ }\r
+ else\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);\r
+ } \r
+ tone_idx = n%20;\r
+ if ((n>=PSD_skip_start) && (n<PSD_skip_stop))\r
+ { \r
+ PSD_report[n] = initial_gain_psd;//SSBT;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));\r
+ }\r
+ else\r
+ {\r
+ PSD_report_tmp = GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);\r
+\r
+ if ( PSD_report_tmp > PSD_report[n])\r
+ PSD_report[n] = PSD_report_tmp;\r
+ \r
+ }\r
+ }\r
+\r
+ PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);\r
+ \r
+ //----end\r
+ //1 Turn on RX\r
+ //Rx AGC on\r
+ ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);\r
+ ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);\r
+ //CCK on\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);\r
+ //1 Turn on TX\r
+ //Resume TX Queue\r
+ ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);\r
+ //Turn on 3-wire\r
+ ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);\r
+ //1 Restore Current Settings\r
+ //Resume DIG\r
+ pDM_Odm->bDMInitialGainEnable= TRUE;\r
+ //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain);\r
+ ODM_Write_DIG(pDM_Odm,(u1Byte) initial_gain);\r
+ // restore originl center frequency\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);\r
+ if(pDM_Odm->SupportICType == ODM_RTL8192D)\r
+ {\r
+ if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))\r
+ {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord, SYN_RF25);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord, SYN_RF26);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord, SYN_RF27);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C);\r
+ }\r
+ else // DualMAC_DualPHY\r
+ {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord, SYN_RF25);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord, SYN_RF26);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord, SYN_RF27);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C);\r
+ }\r
+ }\r
+ //Turn on CCA\r
+ ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);\r
+ //Restore RX idle low power\r
+ if(RxIdleLowPwr == TRUE)\r
+ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);\r
+ \r
+ psd_cnt++;\r
+ //gPrint("psd cnt=%d\n", psd_cnt);\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));\r
+ if (psd_cnt < ReScan)\r
+ {\r
+ ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval); //ms\r
+ }\r
+ else\r
+ { \r
+ psd_cnt = 0;\r
+ for(i=0;i<80;i++)\r
+ RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("psd_report[%d]= %d \n", 2402+i, PSD_report[i]));\r
+ //DbgPrint("psd_report[%d]= %d \n", 2402+i, PSD_report[i]);\r
+\r
+ GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);\r
+\r
+ }\r
+}\r
+\r
+void odm_Write_RXHP(\r
+ IN PVOID pDM_VOID)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;\r
+ u4Byte currentIGI;\r
+\r
+ if(pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);\r
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); \r
+ }\r
+ \r
+ if(pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th)\r
+{\r
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th); // RegC54[9:8]=2'b11: AGC Flow 3\r
+ }\r
+\r
+ if(pRX_HP_Table->RXHP_flag == 0)\r
+ {\r
+ pRX_HP_Table->Cur_IGI = 0x20;\r
+ }\r
+ else\r
+ {\r
+ currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);\r
+ if(currentIGI<0x50)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);\r
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); \r
+ }\r
+ }\r
+ pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI;\r
+ pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th;\r
+\r
+}\r
+\r
+\r
+void odm_RXHP(\r
+ IN PVOID pDM_VOID)\r
+{\r
+#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTER Adapter = pDM_Odm->Adapter;\r
+ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);\r
+ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;\r
+ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;\r
+ PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_FALSEALMCNT);\r
+ \r
+ u1Byte i, j, sum;\r
+ u1Byte Is40MHz;\r
+ s1Byte Intf_diff_idx, MIN_Intf_diff_idx = 16; \r
+ s4Byte cur_channel; \r
+ u1Byte ch_map_intf_5M[17] = {0}; \r
+ static u4Byte FA_TH = 0; \r
+ static u1Byte psd_intf_flag = 0;\r
+ static s4Byte curRssi = 0; \r
+ static s4Byte preRssi = 0; \r
+ static u1Byte PSDTriggerCnt = 1;\r
+ \r
+ u1Byte RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31); // for debug!!\r
+\r
+#if(DEV_BUS_TYPE == RT_USB_INTERFACE) \r
+ static s8Byte lastTxOkCnt = 0, lastRxOkCnt = 0; \r
+ s8Byte curTxOkCnt, curRxOkCnt;\r
+ s8Byte curTPOkCnt;\r
+ s8Byte TP_Acc3, TP_Acc5;\r
+ static s8Byte TP_Buff[5] = {0};\r
+ static u1Byte pre_state = 0, pre_state_flag = 0;\r
+ static u1Byte Intf_HighTP_flag = 0, De_counter = 16; \r
+ static u1Byte TP_Degrade_flag = 0;\r
+#endif \r
+ static u1Byte LatchCnt = 0;\r
+ \r
+ if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E))\r
+ return;\r
+ //AGC RX High Power Mode is only applied on 2G band in 92D!!!\r
+ if(pDM_Odm->SupportICType == ODM_RTL8192D)\r
+ {\r
+ if(*(pDM_Odm->pBandType) != ODM_BAND_2_4G)\r
+ return;\r
+ }\r
+\r
+ if(!(pDM_Odm->SupportAbility & ODM_BB_RXHP))\r
+ return;\r
+\r
+\r
+ //RX HP ON/OFF\r
+ if(RX_HP_enable == 1)\r
+ pRX_HP_Table->RXHP_enable = FALSE;\r
+ else\r
+ pRX_HP_Table->RXHP_enable = TRUE;\r
+\r
+ if(pRX_HP_Table->RXHP_enable == FALSE)\r
+ {\r
+ if(pRX_HP_Table->RXHP_flag == 1)\r
+ {\r
+ pRX_HP_Table->RXHP_flag = 0;\r
+ psd_intf_flag = 0;\r
+ }\r
+ return;\r
+ }\r
+\r
+#if(DEV_BUS_TYPE == RT_USB_INTERFACE) \r
+ //2 Record current TP for USB interface\r
+ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;\r
+ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;\r
+ lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);\r
+ lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);\r
+\r
+ curTPOkCnt = curTxOkCnt+curRxOkCnt;\r
+ TP_Buff[0] = curTPOkCnt; // current TP \r
+ TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3);\r
+ TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5);\r
+ \r
+ if(TP_Acc5 < 1000)\r
+ pRX_HP_Table->TP_Mode = Idle_Mode;\r
+ else if((1000 < TP_Acc5)&&(TP_Acc5 < 3750000))\r
+ pRX_HP_Table->TP_Mode = Low_TP_Mode;\r
+ else\r
+ pRX_HP_Table->TP_Mode = High_TP_Mode;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode));\r
+ // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing.\r
+ // When LatchCnt = 0, we would Get PSD result.\r
+ if(TP_Degrade_flag == 1)\r
+ {\r
+ LatchCnt--;\r
+ if(LatchCnt == 0)\r
+ {\r
+ TP_Degrade_flag = 0;\r
+ }\r
+ }\r
+ // When PSD function triggered by TP degrade 20%, and Interference Flag = 1\r
+ // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down.\r
+ if(Intf_HighTP_flag == 1)\r
+ {\r
+ De_counter--;\r
+ if(De_counter == 0)\r
+ {\r
+ Intf_HighTP_flag = 0;\r
+ psd_intf_flag = 0;\r
+ }\r
+ }\r
+#endif\r
+\r
+ //2 AGC RX High Power Mode by PSD only applied to STA Mode\r
+ //3 NOT applied 1. Ad Hoc Mode.\r
+ //3 NOT applied 2. AP Mode\r
+ if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter)))\r
+ { \r
+ Is40MHz = *(pDM_Odm->pBandWidth);\r
+ curRssi = pDM_Odm->RSSI_Min;\r
+ cur_channel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f;\r
+\r
+ /* check illegal channel and bandwidth */\r
+ if (Is40MHz && ((cur_channel < 3) || (cur_channel > 12))) {\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("illegal channel setting, 40MHz channel = %d\n", cur_channel));\r
+ return;\r
+ }\r
+ \r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag));\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all));\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi));\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel));\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz));\r
+ //2 PSD function would be triggered \r
+ //3 1. Every 4 sec for PCIE\r
+ //3 2. Before TP Mode (Idle TP<4kbps) for USB\r
+ //3 3. After TP Mode (High TP) for USB \r
+ if((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0)) // Only RSSI>TH and RX_HP_flag=0 will Do PSD process \r
+ {\r
+#if (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+ //2 Before TP Mode ==> PSD would be trigger every 4 sec\r
+ if(pRX_HP_Table->TP_Mode == Idle_Mode) //2.1 less wlan traffic <4kbps\r
+ {\r
+#endif\r
+ if(PSDTriggerCnt == 1) \r
+ { \r
+ odm_PSD_RXHP(pDM_Odm);\r
+ pRX_HP_Table->PSD_func_trigger = 1;\r
+ PSDTriggerCnt = 0;\r
+ }\r
+ else\r
+ {\r
+ PSDTriggerCnt++;\r
+ }\r
+#if(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+ } \r
+ //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function\r
+ if(pRX_HP_Table->TP_Mode == High_TP_Mode)\r
+ {\r
+ if((pre_state_flag == 0)&&(LatchCnt == 0)) \r
+ {\r
+ // TP var < 5%\r
+ if((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3)))\r
+ {\r
+ pre_state++;\r
+ if(pre_state == 3) // hit pre_state condition => consecutive 3 times\r
+ {\r
+ pre_state_flag = 1;\r
+ pre_state = 0;\r
+ }\r
+\r
+ }\r
+ else\r
+ {\r
+ pre_state = 0;\r
+ }\r
+ }\r
+ //3 If pre_state_flag=1 ==> start to monitor TP degrade 20%\r
+ if(pre_state_flag == 1) \r
+ {\r
+ if(((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3)) // degrade 20%\r
+ {\r
+ odm_PSD_RXHP(pDM_Odm);\r
+ pRX_HP_Table->PSD_func_trigger = 1;\r
+ TP_Degrade_flag = 1;\r
+ LatchCnt = 2;\r
+ pre_state_flag = 0;\r
+ }\r
+ else if(((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2])\r
+ {\r
+ odm_PSD_RXHP(pDM_Odm);\r
+ pRX_HP_Table->PSD_func_trigger = 1;\r
+ TP_Degrade_flag = 1;\r
+ LatchCnt = 2;\r
+ pre_state_flag = 0;\r
+ }\r
+ else if(((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3])\r
+ {\r
+ odm_PSD_RXHP(pDM_Odm);\r
+ pRX_HP_Table->PSD_func_trigger = 1;\r
+ TP_Degrade_flag = 1;\r
+ LatchCnt = 2;\r
+ pre_state_flag = 0;\r
+ }\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+#if (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+ for (i=0;i<4;i++)\r
+ {\r
+ TP_Buff[4-i] = TP_Buff[3-i];\r
+ }\r
+#endif\r
+ //2 Update PSD bitmap according to PSD report \r
+ if((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0))\r
+ { \r
+ //2 Separate 80M bandwidth into 16 group with smaller 5M BW.\r
+ for (i = 0 ; i < 16 ; i++)\r
+ {\r
+ sum = 0;\r
+ for(j = 0; j < 5 ; j++)\r
+ sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j];\r
+ \r
+ if(sum < 5)\r
+ {\r
+ ch_map_intf_5M[i] = 1; // interference flag\r
+ }\r
+ }\r
+ //=============just for debug=========================\r
+ //for(i=0;i<16;i++)\r
+ //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]);\r
+ //===============================================\r
+ //2 Mask target channel 5M index\r
+ for(i = 0; i < (4+4*Is40MHz) ; i++)\r
+ {\r
+ ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0; \r
+ }\r
+ \r
+ psd_intf_flag = 0;\r
+ for(i = 0; i < 16; i++)\r
+ {\r
+ if(ch_map_intf_5M[i] == 1)\r
+ {\r
+ psd_intf_flag = 1; // interference is detected!!! \r
+ break;\r
+ }\r
+ }\r
+ \r
+#if (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+ if(pRX_HP_Table->TP_Mode!=Idle_Mode)\r
+ {\r
+ if(psd_intf_flag == 1) // to avoid psd_intf_flag always 1\r
+ {\r
+ Intf_HighTP_flag = 1;\r
+ De_counter = 32; // 0x1E -> 0x3E needs 32 times by each IGI step =1\r
+ }\r
+ }\r
+#endif\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag));\r
+ //2 Distance between target channel and interference\r
+ for(i = 0; i < 16; i++)\r
+ {\r
+ if(ch_map_intf_5M[i] == 1)\r
+ {\r
+ Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz)); \r
+ if(Intf_diff_idx < MIN_Intf_diff_idx)\r
+ MIN_Intf_diff_idx = Intf_diff_idx; // the min difference index between interference and target\r
+ }\r
+ }\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx)); \r
+ //2 Choose False Alarm Threshold\r
+ switch (MIN_Intf_diff_idx){\r
+ case 0: \r
+ case 1:\r
+ case 2:\r
+ case 3: \r
+ FA_TH = FA_RXHP_TH1; \r
+ break;\r
+ case 4: // CH5\r
+ case 5: // CH6\r
+ FA_TH = FA_RXHP_TH2; \r
+ break;\r
+ case 6: // CH7\r
+ case 7: // CH8\r
+ FA_TH = FA_RXHP_TH3;\r
+ break; \r
+ case 8: // CH9\r
+ case 9: //CH10\r
+ FA_TH = FA_RXHP_TH4;\r
+ break; \r
+ case 10:\r
+ case 11:\r
+ case 12:\r
+ case 13: \r
+ case 14:\r
+ case 15: \r
+ FA_TH = FA_RXHP_TH5;\r
+ break; \r
+ } \r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH));\r
+ pRX_HP_Table->PSD_func_trigger = 0;\r
+ }\r
+ //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode\r
+ if(pRX_HP_Table->RXHP_flag == 1)\r
+ {\r
+ if ((curRssi > 80)&&(preRssi < 80))\r
+ { \r
+ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;\r
+ }\r
+ else if ((curRssi < 80)&&(preRssi > 80))\r
+ {\r
+ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;\r
+ }\r
+ else if ((curRssi > 72)&&(preRssi < 72))\r
+ {\r
+ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;\r
+ }\r
+ else if ((curRssi < 72)&&( preRssi > 72))\r
+ {\r
+ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;\r
+ }\r
+ else if (curRssi < 68) //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode\r
+ {\r
+ pRX_HP_Table->Cur_pw_th = pw_th_10dB;\r
+ pRX_HP_Table->RXHP_flag = 0; // Back to Normal DIG Mode \r
+ psd_intf_flag = 0;\r
+ }\r
+ }\r
+ else // pRX_HP_Table->RXHP_flag == 0\r
+ {\r
+ //1 Decide whether to enter AGC RX High Power Mode\r
+ if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) && \r
+ (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max))\r
+ {\r
+ if (curRssi > 80)\r
+ {\r
+ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;\r
+ }\r
+ else if (curRssi > 72) \r
+ {\r
+ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;\r
+ }\r
+ else\r
+ {\r
+ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;\r
+ }\r
+ pRX_HP_Table->Cur_pw_th = pw_th_16dB; //RegC54[9:8]=2'b11: to enter AGC Flow 3\r
+ pRX_HP_Table->First_time_enter = TRUE;\r
+ pRX_HP_Table->RXHP_flag = 1; // RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode\r
+ }\r
+ }\r
+ preRssi = curRssi; \r
+ odm_Write_RXHP(pDM_Odm); \r
+ }\r
+#endif //#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
+#endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
+}\r
+\r
+\r
+VOID\r
+odm_PSD_RXHPCallback(\r
+ PRT_TIMER pTimer\r
+)\r
+{\r
+ PADAPTER Adapter = (PADAPTER)pTimer->Adapter;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;\r
+ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;\r
+ \r
+#if DEV_BUS_TYPE==RT_PCI_INTERFACE\r
+ #if USE_WORKITEM\r
+ ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);\r
+ #else\r
+ odm_PSD_RXHP(pDM_Odm);\r
+ #endif\r
+#else\r
+ ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);\r
+#endif\r
+ \r
+ }\r
+\r
+VOID\r
+odm_PSD_RXHPWorkitemCallback(\r
+ IN PVOID pContext\r
+ )\r
+{\r
+ PADAPTER pAdapter = (PADAPTER)pContext;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;\r
+ \r
+ odm_PSD_RXHP(pDM_Odm);\r
+}\r
+\r
+#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+\r
+\r
+ \r
projects / firefly-linux-kernel-4.4.55.git / blobdiff