--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ * \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+//============================================================\r
+// File Name: odm_reg.h\r
+//\r
+// Description:\r
+//\r
+// This file is for general register definition.\r
+//\r
+//\r
+//============================================================\r
+#ifndef __HAL_ODM_REG_H__\r
+#define __HAL_ODM_REG_H__\r
+\r
+//\r
+// Register Definition\r
+//\r
+\r
+//MAC REG\r
+#define ODM_BB_RESET 0x002\r
+#define ODM_DUMMY 0x4fe\r
+#define RF_T_METER_OLD 0x24\r
+#define RF_T_METER_NEW 0x42\r
+\r
+#define ODM_EDCA_VO_PARAM 0x500\r
+#define ODM_EDCA_VI_PARAM 0x504\r
+#define ODM_EDCA_BE_PARAM 0x508\r
+#define ODM_EDCA_BK_PARAM 0x50C\r
+#define ODM_TXPAUSE 0x522\r
+\r
+//BB REG\r
+#define ODM_FPGA_PHY0_PAGE8 0x800\r
+#define ODM_PSD_SETTING 0x808\r
+#define ODM_AFE_SETTING 0x818\r
+#define ODM_TXAGC_B_6_18 0x830\r
+#define ODM_TXAGC_B_24_54 0x834\r
+#define ODM_TXAGC_B_MCS32_5 0x838\r
+#define ODM_TXAGC_B_MCS0_MCS3 0x83c\r
+#define ODM_TXAGC_B_MCS4_MCS7 0x848\r
+#define ODM_TXAGC_B_MCS8_MCS11 0x84c\r
+#define ODM_ANALOG_REGISTER 0x85c\r
+#define ODM_RF_INTERFACE_OUTPUT 0x860\r
+#define ODM_TXAGC_B_MCS12_MCS15 0x868\r
+#define ODM_TXAGC_B_11_A_2_11 0x86c\r
+#define ODM_AD_DA_LSB_MASK 0x874\r
+#define ODM_ENABLE_3_WIRE 0x88c\r
+#define ODM_PSD_REPORT 0x8b4\r
+#define ODM_R_ANT_SELECT 0x90c\r
+#define ODM_CCK_ANT_SELECT 0xa07\r
+#define ODM_CCK_PD_THRESH 0xa0a\r
+#define ODM_CCK_RF_REG1 0xa11\r
+#define ODM_CCK_MATCH_FILTER 0xa20\r
+#define ODM_CCK_RAKE_MAC 0xa2e\r
+#define ODM_CCK_CNT_RESET 0xa2d\r
+#define ODM_CCK_TX_DIVERSITY 0xa2f\r
+#define ODM_CCK_FA_CNT_MSB 0xa5b\r
+#define ODM_CCK_FA_CNT_LSB 0xa5c\r
+#define ODM_CCK_NEW_FUNCTION 0xa75\r
+#define ODM_OFDM_PHY0_PAGE_C 0xc00\r
+#define ODM_OFDM_RX_ANT 0xc04\r
+#define ODM_R_A_RXIQI 0xc14\r
+#define ODM_R_A_AGC_CORE1 0xc50\r
+#define ODM_R_A_AGC_CORE2 0xc54\r
+#define ODM_R_B_AGC_CORE1 0xc58\r
+#define ODM_R_AGC_PAR 0xc70\r
+#define ODM_R_HTSTF_AGC_PAR 0xc7c\r
+#define ODM_TX_PWR_TRAINING_A 0xc90\r
+#define ODM_TX_PWR_TRAINING_B 0xc98\r
+#define ODM_OFDM_FA_CNT1 0xcf0\r
+#define ODM_OFDM_PHY0_PAGE_D 0xd00\r
+#define ODM_OFDM_FA_CNT2 0xda0\r
+#define ODM_OFDM_FA_CNT3 0xda4\r
+#define ODM_OFDM_FA_CNT4 0xda8\r
+#define ODM_TXAGC_A_6_18 0xe00\r
+#define ODM_TXAGC_A_24_54 0xe04\r
+#define ODM_TXAGC_A_1_MCS32 0xe08\r
+#define ODM_TXAGC_A_MCS0_MCS3 0xe10\r
+#define ODM_TXAGC_A_MCS4_MCS7 0xe14\r
+#define ODM_TXAGC_A_MCS8_MCS11 0xe18\r
+#define ODM_TXAGC_A_MCS12_MCS15 0xe1c\r
+\r
+//RF REG\r
+#define ODM_GAIN_SETTING 0x00\r
+#define ODM_CHANNEL 0x18\r
+#define ODM_RF_T_METER 0x24\r
+#define ODM_RF_T_METER_92D 0x42\r
+#define ODM_RF_T_METER_88E 0x42\r
+#define ODM_RF_T_METER_92E 0x42\r
+#define ODM_RF_T_METER_8812 0x42\r
+\r
+//Ant Detect Reg\r
+#define ODM_DPDT 0x300\r
+\r
+//PSD Init\r
+#define ODM_PSDREG 0x808\r
+\r
+//92D Path Div\r
+#define PATHDIV_REG 0xB30\r
+#define PATHDIV_TRI 0xBA0\r
+\r
+\r
+//\r
+// Bitmap Definition\r
+//\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+// TX AGC \r
+#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20\r
+#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24\r
+#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28\r
+#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c\r
+#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30\r
+#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34\r
+#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38\r
+#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c\r
+#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40\r
+#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44\r
+#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48\r
+#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c\r
+#if defined(CONFIG_WLAN_HAL_8814AE)\r
+#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8\r
+#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc\r
+#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0\r
+#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4\r
+#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8\r
+#endif\r
+#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20\r
+#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24\r
+#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28\r
+#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c\r
+#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30\r
+#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34\r
+#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38\r
+#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c\r
+#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40\r
+#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44\r
+#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48\r
+#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c\r
+#if defined(CONFIG_WLAN_HAL_8814AE)\r
+#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8\r
+#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc\r
+#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0\r
+#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4\r
+#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8\r
+#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820\r
+#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824\r
+#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828\r
+#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c\r
+#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830\r
+#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834\r
+#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838\r
+#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c\r
+#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840\r
+#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844\r
+#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848\r
+#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c\r
+#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8\r
+#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc\r
+#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0\r
+#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4\r
+#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8\r
+#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20\r
+#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24\r
+#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28\r
+#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c\r
+#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30\r
+#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34\r
+#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38\r
+#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c\r
+#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40\r
+#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44\r
+#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48\r
+#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c\r
+#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8\r
+#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc\r
+#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0\r
+#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4\r
+#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8\r
+#endif\r
+\r
+#define bTxAGC_byte0_Jaguar 0xff\r
+#define bTxAGC_byte1_Jaguar 0xff00\r
+#define bTxAGC_byte2_Jaguar 0xff0000\r
+#define bTxAGC_byte3_Jaguar 0xff000000\r
+#endif\r
+\r
+#define BIT_FA_RESET BIT0\r
+\r
+\r
+\r
+#endif\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff