--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __PHYDMRAINFO_H__\r
+#define __PHYDMRAINFO_H__\r
+\r
+/*#define RAINFO_VERSION "2.0" //2014.11.04*/\r
+/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/\r
+/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/\r
+#define RAINFO_VERSION "3.2" /*2015.01.14 Dino*/\r
+\r
+#define HIGH_RSSI_THRESH 50\r
+#define LOW_RSSI_THRESH 20\r
+\r
+#define ACTIVE_TP_THRESHOLD 150\r
+#define RA_RETRY_DESCEND_NUM 2\r
+#define RA_RETRY_LIMIT_LOW 4\r
+#define RA_RETRY_LIMIT_HIGH 32\r
+\r
+#define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F)\r
+#define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8821B|ODM_RTL8822B)\r
+\r
+#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL\r
+#define RAINFO_STBC_STATE BIT1\r
+//#define RAINFO_LDPC_STATE BIT2\r
+#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection\r
+#define RAINFO_SHURTCUT_STATE BIT3\r
+#define RAINFO_SHURTCUT_FLAG BIT4\r
+#define RAINFO_INIT_RSSI_RATE_STATE BIT5\r
+#define RAINFO_BF_STATE BIT6\r
+#define RAINFO_BE_TX_STATE BIT7 // 1:TX\r
+\r
+#define RA_MASK_CCK 0xf\r
+#define RA_MASK_OFDM 0xff0\r
+#define RA_MASK_HT1SS 0xff000\r
+#define RA_MASK_HT2SS 0xff00000\r
+/*#define RA_MASK_MCS3SS */\r
+#define RA_MASK_HT4SS 0xff0\r
+#define RA_MASK_VHT1SS 0x3ff000\r
+#define RA_MASK_VHT2SS 0xffc00000\r
+\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8881A |ODM_RTL8192E |ODM_RTL8812 |ODM_RTL8814A|ODM_RTL8822B)\r
+#define RA_FIRST_MACID 1\r
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8703B)\r
+#define RA_FIRST_MACID 0\r
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+/*#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8723B|ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8703B) */\r
+#define RA_FIRST_MACID 0\r
+#endif\r
+\r
+\r
+#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit\r
+\r
+#define DM_RATR_STA_INIT 0\r
+#define DM_RATR_STA_HIGH 1\r
+#define DM_RATR_STA_MIDDLE 2\r
+#define DM_RATR_STA_LOW 3\r
+#if(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
+#define DM_RATR_STA_ULTRA_LOW 4\r
+#endif\r
+\r
+#define DM_RA_RATE_UP 1\r
+#define DM_RA_RATE_DOWN 2\r
+\r
+typedef enum _phydm_arfr_num {\r
+ ARFR_0_RATE_ID = 0x9,\r
+ ARFR_1_RATE_ID = 0xa,\r
+ ARFR_2_RATE_ID = 0xb,\r
+ ARFR_3_RATE_ID = 0xc,\r
+ ARFR_4_RATE_ID = 0xd,\r
+ ARFR_5_RATE_ID = 0xe\r
+} PHYDM_RA_ARFR_NUM_E;\r
+\r
+typedef enum _Phydm_ra_dbg_para {\r
+ RADBG_RTY_PENALTY = 1, //u8\r
+ RADBG_N_HIGH = 2,\r
+ RADBG_N_LOW = 3,\r
+ RADBG_TRATE_UP_TABLE = 4,\r
+ RADBG_TRATE_DOWN_TABLE = 5,\r
+ RADBG_TRYING_NECESSARY = 6,\r
+ RADBG_TDROPING_NECESSARY = 7,\r
+ RADBG_RATE_UP_RTY_RATIO = 8, //u8\r
+ RADBG_RATE_DOWN_RTY_RATIO = 9, //u8\r
+\r
+ RADBG_DEBUG_MONITOR1 = 0xc,\r
+ RADBG_DEBUG_MONITOR2 = 0xd,\r
+ RADBG_DEBUG_MONITOR3 = 0xe,\r
+ RADBG_DEBUG_MONITOR4 = 0xf,\r
+ NUM_RA_PARA\r
+} PHYDM_RA_DBG_PARA_E;\r
+\r
+\r
+#if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA\r
+typedef struct _ODM_RA_Info_ {\r
+ u1Byte RateID;\r
+ u4Byte RateMask;\r
+ u4Byte RAUseRate;\r
+ u1Byte RateSGI;\r
+ u1Byte RssiStaRA;\r
+ u1Byte PreRssiStaRA;\r
+ u1Byte SGIEnable;\r
+ u1Byte DecisionRate;\r
+ u1Byte PreRate;\r
+ u1Byte HighestRate;\r
+ u1Byte LowestRate;\r
+ u4Byte NscUp;\r
+ u4Byte NscDown;\r
+ u2Byte RTY[5];\r
+ u4Byte TOTAL;\r
+ u2Byte DROP;\r
+ u1Byte Active;\r
+ u2Byte RptTime;\r
+ u1Byte RAWaitingCounter;\r
+ u1Byte RAPendingCounter;\r
+#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!\r
+ u1Byte PTActive; // on or off\r
+ u1Byte PTTryState; // 0 trying state, 1 for decision state\r
+ u1Byte PTStage; // 0~6\r
+ u1Byte PTStopCount; //Stop PT counter\r
+ u1Byte PTPreRate; // if rate change do PT\r
+ u1Byte PTPreRssi; // if RSSI change 5% do PT\r
+ u1Byte PTModeSS; // decide whitch rate should do PT\r
+ u1Byte RAstage; // StageRA, decide how many times RA will be done between PT\r
+ u1Byte PTSmoothFactor;\r
+#endif\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\r
+ u1Byte RateDownCounter;\r
+ u1Byte RateUpCounter;\r
+ u1Byte RateDirection;\r
+ u1Byte BoundingType;\r
+ u1Byte BoundingCounter;\r
+ u1Byte BoundingLearningTime;\r
+ u1Byte RateDownStartTime;\r
+#endif\r
+} ODM_RA_INFO_T, *PODM_RA_INFO_T;\r
+#endif\r
+\r
+\r
+typedef struct _Rate_Adaptive_Table_ {\r
+ u1Byte firstconnect;\r
+#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)\r
+ BOOLEAN PT_collision_pre;\r
+#endif\r
+\r
+#if (defined(CONFIG_RA_DBG_CMD))\r
+ BOOLEAN is_ra_dbg_init;\r
+\r
+ u1Byte RTY_P[ODM_NUM_RATE_IDX];\r
+ u1Byte RTY_P_default[ODM_NUM_RATE_IDX];\r
+ BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX];\r
+\r
+ u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];\r
+ u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];\r
+ BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];\r
+\r
+ u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];\r
+ u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];\r
+ BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];\r
+\r
+ BOOLEAN RA_Para_feedback_req;\r
+\r
+ u1Byte para_idx;\r
+ u1Byte rate_idx;\r
+ u1Byte value;\r
+ u2Byte value_16;\r
+ u1Byte rate_length;\r
+#endif\r
+ u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];\r
+\r
+ #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))\r
+ u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];\r
+ u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; \r
+ u1Byte retry_descend_num;\r
+ u1Byte retrylimit_low;\r
+ u1Byte retrylimit_high;\r
+ #endif\r
+\r
+\r
+} RA_T, *pRA_T;\r
+\r
+typedef struct _ODM_RATE_ADAPTIVE {\r
+ u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver\r
+ u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH\r
+ u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW\r
+ u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW\r
+\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
+ u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC\r
+ BOOLEAN bLowerRtsRate;\r
+#endif\r
+\r
+#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
+ u1Byte RtsThres;\r
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)\r
+ BOOLEAN bUseLdpc;\r
+#else\r
+ u1Byte UltraLowRSSIThresh;\r
+ u4Byte LastRATR; // RATR Register Content\r
+#endif\r
+\r
+} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;\r
+\r
+VOID\r
+ODM_C2HRaParaReportHandler(\r
+ IN PVOID pDM_VOID,\r
+ IN pu1Byte CmdBuf,\r
+ IN u1Byte CmdLen\r
+);\r
+\r
+VOID\r
+odm_RA_ParaAdjust_Send_H2C(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RA_debug(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte *const dm_value\r
+);\r
+\r
+VOID\r
+odm_RA_ParaAdjust_init(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RA_ParaAdjust(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+phydm_ra_dynamic_retry_count(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+phydm_ra_dynamic_retry_limit(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+phydm_ra_dynamic_rate_id_on_assoc(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte wireless_mode,\r
+ IN u1Byte init_rate_id\r
+);\r
+\r
+VOID\r
+phydm_c2h_ra_report_handler(\r
+ IN PVOID pDM_VOID,\r
+ IN pu1Byte CmdBuf,\r
+ IN u1Byte CmdLen\r
+);\r
+\r
+VOID\r
+phydm_ra_info_init(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RSSIMonitorInit(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RSSIMonitorCheck(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+s4Byte\r
+phydm_FindMinimumRSSI(\r
+IN PDM_ODM_T pDM_Odm,\r
+IN PADAPTER pAdapter,\r
+IN OUT BOOLEAN *pbLink_temp\r
+\r
+ );\r
+#endif\r
+\r
+VOID\r
+odm_RSSIMonitorCheckMP(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RSSIMonitorCheckCE(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RSSIMonitorCheckAP(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+\r
+VOID\r
+odm_RateAdaptiveMaskInit(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RefreshRateAdaptiveMask(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RefreshRateAdaptiveMaskMP(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RefreshRateAdaptiveMaskCE(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RefreshRateAdaptiveMaskAPADSL(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+BOOLEAN\r
+ODM_RAStateCheck(\r
+ IN PVOID pDM_VOID,\r
+ IN s4Byte RSSI,\r
+ IN BOOLEAN bForceUpdate,\r
+ OUT pu1Byte pRATRState\r
+);\r
+\r
+VOID\r
+odm_RefreshBasicRateMask(\r
+ IN PVOID pDM_VOID\r
+);\r
+VOID\r
+ODM_RAPostActionOnAssoc(\r
+ IN PVOID pDM_Odm\r
+);\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\r
+\r
+u1Byte\r
+odm_Find_RTS_Rate(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Tx_Rate,\r
+ IN BOOLEAN bErpProtect\r
+);\r
+\r
+VOID\r
+ODM_UpdateNoisyState(\r
+ IN PVOID pDM_VOID,\r
+ IN BOOLEAN bNoisyStateFromC2H\r
+);\r
+\r
+u4Byte\r
+Set_RA_DM_Ratrbitmap_by_Noisy(\r
+ IN PVOID pDM_VOID,\r
+ IN WIRELESS_MODE WirelessMode,\r
+ IN u4Byte ratr_bitmap,\r
+ IN u1Byte rssi_level\r
+);\r
+\r
+VOID\r
+ODM_UpdateInitRate(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Rate\r
+);\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+\r
+VOID\r
+odm_RSSIDumpToRegister(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+odm_RefreshLdpcRtsMP(\r
+ IN PADAPTER pAdapter,\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN u1Byte mMacId,\r
+ IN u1Byte IOTPeer,\r
+ IN s4Byte UndecoratedSmoothedPWDB\r
+);\r
+\r
+VOID\r
+ODM_DynamicARFBSelect(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte rate,\r
+ IN BOOLEAN Collision_State\r
+);\r
+\r
+VOID\r
+ODM_RateAdaptiveStateApInit(\r
+ IN PVOID PADAPTER_VOID,\r
+ IN PRT_WLAN_STA pEntry\r
+);\r
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+\r
+static void\r
+FindMinimumRSSI(\r
+ IN PADAPTER pAdapter\r
+);\r
+\r
+u8Byte\r
+PhyDM_Get_Rate_Bitmap_Ex(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte macid,\r
+ IN u8Byte ra_mask,\r
+ IN u1Byte rssi_level,\r
+ OUT u8Byte *dm_RA_Mask,\r
+ OUT u1Byte *dm_RteID\r
+);\r
+u4Byte\r
+ODM_Get_Rate_Bitmap(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte macid,\r
+ IN u4Byte ra_mask,\r
+ IN u1Byte rssi_level\r
+);\r
+void phydm_ra_rssi_rpt_wk(PVOID pContext);\r
+\r
+#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/\r
+\r
+#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/\r
+\r
+#endif /*#ifndef __ODMRAINFO_H__*/\r
+\r
+\r
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