--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ * \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __PHYDMPREDEFINE_H__\r
+#define __PHYDMPREDEFINE_H__\r
+\r
+//1 ============================================================\r
+//1 Definition \r
+//1 ============================================================\r
+\r
+//Max path of IC\r
+#define MAX_PATH_NUM_92CS 2\r
+#define MAX_PATH_NUM_8188E 1\r
+#define MAX_PATH_NUM_8192E 2\r
+#define MAX_PATH_NUM_8723B 1\r
+#define MAX_PATH_NUM_8812A 2\r
+#define MAX_PATH_NUM_8821A 1\r
+#define MAX_PATH_NUM_8814A 4\r
+#define MAX_PATH_NUM_8822B 2\r
+#define MAX_PATH_NUM_8821B 2\r
+#define MAX_PATH_NUM_8703B 1\r
+#define MAX_PATH_NUM_8188F 1\r
+\r
+//Max RF path\r
+#define ODM_RF_PATH_MAX 2\r
+#define ODM_RF_PATH_MAX_JAGUAR 4\r
+\r
+//number of entry\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
+ #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/\r
+ #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM\r
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
+ #define ASSOCIATE_ENTRY_NUM NUM_STAT\r
+ #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1)\r
+#else\r
+ #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1)\r
+#endif\r
+\r
+/* -----MGN rate--------------------------------- */\r
+\r
+#define ODM_MGN_1M 0x02\r
+#define ODM_MGN_2M 0x04\r
+#define ODM_MGN_5_5M 0x0b\r
+#define ODM_MGN_11M 0x16\r
+\r
+#define ODM_MGN_6M 0x0c\r
+#define ODM_MGN_9M 0x12\r
+#define ODM_MGN_12M 0x18\r
+#define ODM_MGN_18M 0x24\r
+#define ODM_MGN_24M 0x30\r
+#define ODM_MGN_36M 0x48\r
+#define ODM_MGN_48M 0x60\r
+#define ODM_MGN_54M 0x6c\r
+\r
+/*TxHT = 1*/\r
+#define ODM_MGN_MCS0 0x80\r
+#define ODM_MGN_MCS1 0x81\r
+#define ODM_MGN_MCS2 0x82\r
+#define ODM_MGN_MCS3 0x83\r
+#define ODM_MGN_MCS4 0x84\r
+#define ODM_MGN_MCS5 0x85\r
+#define ODM_MGN_MCS6 0x86\r
+#define ODM_MGN_MCS7 0x87\r
+#define ODM_MGN_MCS8 0x88\r
+#define ODM_MGN_MCS9 0x89\r
+#define ODM_MGN_MCS10 0x8a\r
+#define ODM_MGN_MCS11 0x8b\r
+#define ODM_MGN_MCS12 0x8c\r
+#define ODM_MGN_MCS13 0x8d\r
+#define ODM_MGN_MCS14 0x8e\r
+#define ODM_MGN_MCS15 0x8f\r
+#define ODM_MGN_VHT1SS_MCS0 0x90\r
+#define ODM_MGN_VHT1SS_MCS1 0x91\r
+#define ODM_MGN_VHT1SS_MCS2 0x92\r
+#define ODM_MGN_VHT1SS_MCS3 0x93\r
+#define ODM_MGN_VHT1SS_MCS4 0x94\r
+#define ODM_MGN_VHT1SS_MCS5 0x95\r
+#define ODM_MGN_VHT1SS_MCS6 0x96\r
+#define ODM_MGN_VHT1SS_MCS7 0x97\r
+#define ODM_MGN_VHT1SS_MCS8 0x98\r
+#define ODM_MGN_VHT1SS_MCS9 0x99\r
+#define ODM_MGN_VHT2SS_MCS0 0x9a\r
+#define ODM_MGN_VHT2SS_MCS1 0x9b\r
+#define ODM_MGN_VHT2SS_MCS2 0x9c\r
+#define ODM_MGN_VHT2SS_MCS3 0x9d\r
+#define ODM_MGN_VHT2SS_MCS4 0x9e\r
+#define ODM_MGN_VHT2SS_MCS5 0x9f\r
+#define ODM_MGN_VHT2SS_MCS6 0xa0\r
+#define ODM_MGN_VHT2SS_MCS7 0xa1\r
+#define ODM_MGN_VHT2SS_MCS8 0xa2\r
+#define ODM_MGN_VHT2SS_MCS9 0xa3\r
+\r
+#define ODM_MGN_MCS0_SG 0xc0\r
+#define ODM_MGN_MCS1_SG 0xc1\r
+#define ODM_MGN_MCS2_SG 0xc2\r
+#define ODM_MGN_MCS3_SG 0xc3\r
+#define ODM_MGN_MCS4_SG 0xc4\r
+#define ODM_MGN_MCS5_SG 0xc5\r
+#define ODM_MGN_MCS6_SG 0xc6\r
+#define ODM_MGN_MCS7_SG 0xc7\r
+#define ODM_MGN_MCS8_SG 0xc8\r
+#define ODM_MGN_MCS9_SG 0xc9\r
+#define ODM_MGN_MCS10_SG 0xca\r
+#define ODM_MGN_MCS11_SG 0xcb\r
+#define ODM_MGN_MCS12_SG 0xcc\r
+#define ODM_MGN_MCS13_SG 0xcd\r
+#define ODM_MGN_MCS14_SG 0xce\r
+#define ODM_MGN_MCS15_SG 0xcf\r
+\r
+/* -----DESC rate--------------------------------- */\r
+\r
+#define ODM_RATEMCS15_SG 0x1c\r
+#define ODM_RATEMCS32 0x20\r
+\r
+\r
+// CCK Rates, TxHT = 0\r
+#define ODM_RATE1M 0x00\r
+#define ODM_RATE2M 0x01\r
+#define ODM_RATE5_5M 0x02\r
+#define ODM_RATE11M 0x03\r
+// OFDM Rates, TxHT = 0\r
+#define ODM_RATE6M 0x04\r
+#define ODM_RATE9M 0x05\r
+#define ODM_RATE12M 0x06\r
+#define ODM_RATE18M 0x07\r
+#define ODM_RATE24M 0x08\r
+#define ODM_RATE36M 0x09\r
+#define ODM_RATE48M 0x0A\r
+#define ODM_RATE54M 0x0B\r
+// MCS Rates, TxHT = 1\r
+#define ODM_RATEMCS0 0x0C\r
+#define ODM_RATEMCS1 0x0D\r
+#define ODM_RATEMCS2 0x0E\r
+#define ODM_RATEMCS3 0x0F\r
+#define ODM_RATEMCS4 0x10\r
+#define ODM_RATEMCS5 0x11\r
+#define ODM_RATEMCS6 0x12\r
+#define ODM_RATEMCS7 0x13\r
+#define ODM_RATEMCS8 0x14\r
+#define ODM_RATEMCS9 0x15\r
+#define ODM_RATEMCS10 0x16\r
+#define ODM_RATEMCS11 0x17\r
+#define ODM_RATEMCS12 0x18\r
+#define ODM_RATEMCS13 0x19\r
+#define ODM_RATEMCS14 0x1A\r
+#define ODM_RATEMCS15 0x1B\r
+#define ODM_RATEMCS16 0x1C\r
+#define ODM_RATEMCS17 0x1D\r
+#define ODM_RATEMCS18 0x1E\r
+#define ODM_RATEMCS19 0x1F\r
+#define ODM_RATEMCS20 0x20\r
+#define ODM_RATEMCS21 0x21\r
+#define ODM_RATEMCS22 0x22\r
+#define ODM_RATEMCS23 0x23\r
+#define ODM_RATEMCS24 0x24\r
+#define ODM_RATEMCS25 0x25\r
+#define ODM_RATEMCS26 0x26\r
+#define ODM_RATEMCS27 0x27\r
+#define ODM_RATEMCS28 0x28\r
+#define ODM_RATEMCS29 0x29\r
+#define ODM_RATEMCS30 0x2A\r
+#define ODM_RATEMCS31 0x2B\r
+#define ODM_RATEVHTSS1MCS0 0x2C\r
+#define ODM_RATEVHTSS1MCS1 0x2D\r
+#define ODM_RATEVHTSS1MCS2 0x2E\r
+#define ODM_RATEVHTSS1MCS3 0x2F\r
+#define ODM_RATEVHTSS1MCS4 0x30\r
+#define ODM_RATEVHTSS1MCS5 0x31\r
+#define ODM_RATEVHTSS1MCS6 0x32\r
+#define ODM_RATEVHTSS1MCS7 0x33\r
+#define ODM_RATEVHTSS1MCS8 0x34\r
+#define ODM_RATEVHTSS1MCS9 0x35\r
+#define ODM_RATEVHTSS2MCS0 0x36\r
+#define ODM_RATEVHTSS2MCS1 0x37\r
+#define ODM_RATEVHTSS2MCS2 0x38\r
+#define ODM_RATEVHTSS2MCS3 0x39\r
+#define ODM_RATEVHTSS2MCS4 0x3A\r
+#define ODM_RATEVHTSS2MCS5 0x3B\r
+#define ODM_RATEVHTSS2MCS6 0x3C\r
+#define ODM_RATEVHTSS2MCS7 0x3D\r
+#define ODM_RATEVHTSS2MCS8 0x3E\r
+#define ODM_RATEVHTSS2MCS9 0x3F\r
+#define ODM_RATEVHTSS3MCS0 0x40\r
+#define ODM_RATEVHTSS3MCS1 0x41\r
+#define ODM_RATEVHTSS3MCS2 0x42\r
+#define ODM_RATEVHTSS3MCS3 0x43\r
+#define ODM_RATEVHTSS3MCS4 0x44\r
+#define ODM_RATEVHTSS3MCS5 0x45\r
+#define ODM_RATEVHTSS3MCS6 0x46\r
+#define ODM_RATEVHTSS3MCS7 0x47\r
+#define ODM_RATEVHTSS3MCS8 0x48\r
+#define ODM_RATEVHTSS3MCS9 0x49\r
+#define ODM_RATEVHTSS4MCS0 0x4A\r
+#define ODM_RATEVHTSS4MCS1 0x4B\r
+#define ODM_RATEVHTSS4MCS2 0x4C\r
+#define ODM_RATEVHTSS4MCS3 0x4D\r
+#define ODM_RATEVHTSS4MCS4 0x4E\r
+#define ODM_RATEVHTSS4MCS5 0x4F\r
+#define ODM_RATEVHTSS4MCS6 0x50\r
+#define ODM_RATEVHTSS4MCS7 0x51\r
+#define ODM_RATEVHTSS4MCS8 0x52\r
+#define ODM_RATEVHTSS4MCS9 0x53\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)\r
+#else\r
+ #if (RTL8192E_SUPPORT == 1)\r
+ #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1)\r
+ #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) \r
+ #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1)\r
+ #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) \r
+ #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1)\r
+ #elif (RTL8812A_SUPPORT == 1)\r
+ #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1)\r
+ #elif(RTL8814A_SUPPORT == 1)\r
+ #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1)\r
+ #else\r
+ #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)\r
+ #endif\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+#define CONFIG_SFW_SUPPORTED\r
+#endif\r
+\r
+//1 ============================================================\r
+//1 enumeration\r
+//1 ============================================================\r
+\r
+\r
+// ODM_CMNINFO_INTERFACE\r
+typedef enum tag_ODM_Support_Interface_Definition\r
+{\r
+ ODM_ITRF_PCIE = 0x1,\r
+ ODM_ITRF_USB = 0x2,\r
+ ODM_ITRF_SDIO = 0x4,\r
+ ODM_ITRF_ALL = 0x7,\r
+}ODM_INTERFACE_E;\r
+\r
+// ODM_CMNINFO_IC_TYPE\r
+typedef enum tag_ODM_Support_IC_Type_Definition\r
+{\r
+ ODM_RTL8192S = BIT0,\r
+ ODM_RTL8192C = BIT1,\r
+ ODM_RTL8192D = BIT2,\r
+ ODM_RTL8723A = BIT3,\r
+ ODM_RTL8188E = BIT4,\r
+ ODM_RTL8812 = BIT5,\r
+ ODM_RTL8821 = BIT6,\r
+ ODM_RTL8192E = BIT7, \r
+ ODM_RTL8723B = BIT8,\r
+ ODM_RTL8814A = BIT9, \r
+ ODM_RTL8881A = BIT10,\r
+ ODM_RTL8821B = BIT11,\r
+ ODM_RTL8822B = BIT12,\r
+ ODM_RTL8703B = BIT13,\r
+ ODM_RTL8195A = BIT14,\r
+ ODM_RTL8188F = BIT15\r
+}ODM_IC_TYPE_E;\r
+\r
+\r
+\r
+\r
+#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F)\r
+#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B)\r
+#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B)\r
+#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A|ODM_RTL8703B|ODM_RTL8188F)\r
+#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A|ODM_RTL8822B)\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+\r
+#ifdef RTK_AC_SUPPORT\r
+#define ODM_IC_11AC_SERIES_SUPPORT 1\r
+#else\r
+#define ODM_IC_11AC_SERIES_SUPPORT 0\r
+#endif\r
+\r
+#define ODM_IC_11N_SERIES_SUPPORT 1\r
+#define ODM_CONFIG_BT_COEXIST 0\r
+\r
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+\r
+#define ODM_IC_11AC_SERIES_SUPPORT 1\r
+#define ODM_IC_11N_SERIES_SUPPORT 1\r
+#define ODM_CONFIG_BT_COEXIST 1\r
+\r
+#else \r
+\r
+#if((RTL8192C_SUPPORT == 1) || (RTL8192D_SUPPORT == 1) || (RTL8723A_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) ||\\r
+(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \\r
+(RTL8188F_SUPPORT == 1))\r
+#define ODM_IC_11N_SERIES_SUPPORT 1\r
+#define ODM_IC_11AC_SERIES_SUPPORT 0\r
+#else\r
+#define ODM_IC_11N_SERIES_SUPPORT 0\r
+#define ODM_IC_11AC_SERIES_SUPPORT 1\r
+#endif\r
+\r
+#ifdef CONFIG_BT_COEXIST\r
+#define ODM_CONFIG_BT_COEXIST 1\r
+#else\r
+#define ODM_CONFIG_BT_COEXIST 0\r
+#endif\r
+\r
+#endif\r
+\r
+\r
+//ODM_CMNINFO_CUT_VER\r
+typedef enum tag_ODM_Cut_Version_Definition\r
+{\r
+ ODM_CUT_A = 0,\r
+ ODM_CUT_B = 1,\r
+ ODM_CUT_C = 2,\r
+ ODM_CUT_D = 3,\r
+ ODM_CUT_E = 4,\r
+ ODM_CUT_F = 5,\r
+\r
+ ODM_CUT_I = 8,\r
+ ODM_CUT_J = 9,\r
+ ODM_CUT_K = 10, \r
+ ODM_CUT_TEST = 15,\r
+}ODM_CUT_VERSION_E;\r
+\r
+// ODM_CMNINFO_FAB_VER\r
+typedef enum tag_ODM_Fab_Version_Definition\r
+{\r
+ ODM_TSMC = 0,\r
+ ODM_UMC = 1,\r
+}ODM_FAB_E;\r
+\r
+// ODM_CMNINFO_RF_TYPE\r
+//\r
+// For example 1T2R (A+AB = BIT0|BIT4|BIT5)\r
+//\r
+typedef enum tag_ODM_RF_Path_Bit_Definition\r
+{\r
+ ODM_RF_A = BIT0,\r
+ ODM_RF_B = BIT1,\r
+ ODM_RF_C = BIT2,\r
+ ODM_RF_D = BIT3,\r
+}ODM_RF_PATH_E;\r
+\r
+typedef enum tag_PHYDM_RF_TX_NUM {\r
+ ODM_1T = 1,\r
+ ODM_2T = 2,\r
+ ODM_3T = 3,\r
+ ODM_4T = 4,\r
+} ODM_RF_TX_NUM_E;\r
+\r
+typedef enum tag_ODM_RF_Type_Definition {\r
+ ODM_1T1R,\r
+ ODM_1T2R,\r
+ ODM_2T2R,\r
+ ODM_2T2R_GREEN,\r
+ ODM_2T3R,\r
+ ODM_2T4R,\r
+ ODM_3T3R,\r
+ ODM_3T4R,\r
+ ODM_4T4R,\r
+ ODM_XTXR\r
+}ODM_RF_TYPE_E;\r
+\r
+\r
+typedef enum tag_ODM_MAC_PHY_Mode_Definition\r
+{\r
+ ODM_SMSP = 0,\r
+ ODM_DMSP = 1,\r
+ ODM_DMDP = 2,\r
+}ODM_MAC_PHY_MODE_E;\r
+\r
+\r
+typedef enum tag_BT_Coexist_Definition\r
+{ \r
+ ODM_BT_BUSY = 1,\r
+ ODM_BT_ON = 2,\r
+ ODM_BT_OFF = 3,\r
+ ODM_BT_NONE = 4,\r
+}ODM_BT_COEXIST_E;\r
+\r
+// ODM_CMNINFO_OP_MODE\r
+typedef enum tag_Operation_Mode_Definition\r
+{\r
+ ODM_NO_LINK = BIT0,\r
+ ODM_LINK = BIT1,\r
+ ODM_SCAN = BIT2,\r
+ ODM_POWERSAVE = BIT3,\r
+ ODM_AP_MODE = BIT4,\r
+ ODM_CLIENT_MODE = BIT5,\r
+ ODM_AD_HOC = BIT6,\r
+ ODM_WIFI_DIRECT = BIT7,\r
+ ODM_WIFI_DISPLAY = BIT8,\r
+}ODM_OPERATION_MODE_E;\r
+\r
+// ODM_CMNINFO_WM_MODE\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
+typedef enum tag_Wireless_Mode_Definition\r
+{\r
+ ODM_WM_UNKNOW = 0x0,\r
+ ODM_WM_B = BIT0,\r
+ ODM_WM_G = BIT1,\r
+ ODM_WM_A = BIT2,\r
+ ODM_WM_N24G = BIT3,\r
+ ODM_WM_N5G = BIT4,\r
+ ODM_WM_AUTO = BIT5,\r
+ ODM_WM_AC = BIT6,\r
+}ODM_WIRELESS_MODE_E;\r
+#else\r
+typedef enum tag_Wireless_Mode_Definition\r
+{\r
+ ODM_WM_UNKNOWN = 0x00,/*0x0*/\r
+ ODM_WM_A = BIT0, /* 0x1*/\r
+ ODM_WM_B = BIT1, /* 0x2*/\r
+ ODM_WM_G = BIT2,/* 0x4*/\r
+ ODM_WM_AUTO = BIT3,/* 0x8*/\r
+ ODM_WM_N24G = BIT4,/* 0x10*/\r
+ ODM_WM_N5G = BIT5,/* 0x20*/\r
+ ODM_WM_AC_5G = BIT6,/* 0x40*/\r
+ ODM_WM_AC_24G = BIT7,/* 0x80*/\r
+ ODM_WM_AC_ONLY = BIT8,/* 0x100*/\r
+ ODM_WM_MAX = BIT11/* 0x800*/\r
+\r
+}ODM_WIRELESS_MODE_E;\r
+#endif\r
+\r
+// ODM_CMNINFO_BAND\r
+typedef enum tag_Band_Type_Definition\r
+{\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+ ODM_BAND_2_4G = BIT0,\r
+ ODM_BAND_5G = BIT1,\r
+#else\r
+ ODM_BAND_2_4G = 0,\r
+ ODM_BAND_5G,\r
+ ODM_BAND_ON_BOTH,\r
+ ODM_BANDMAX\r
+#endif\r
+}ODM_BAND_TYPE_E;\r
+\r
+\r
+// ODM_CMNINFO_SEC_CHNL_OFFSET\r
+typedef enum tag_Secondary_Channel_Offset_Definition\r
+{\r
+ ODM_DONT_CARE = 0,\r
+ ODM_BELOW = 1,\r
+ ODM_ABOVE = 2\r
+}ODM_SEC_CHNL_OFFSET_E;\r
+\r
+// ODM_CMNINFO_SEC_MODE\r
+typedef enum tag_Security_Definition\r
+{\r
+ ODM_SEC_OPEN = 0,\r
+ ODM_SEC_WEP40 = 1,\r
+ ODM_SEC_TKIP = 2,\r
+ ODM_SEC_RESERVE = 3,\r
+ ODM_SEC_AESCCMP = 4,\r
+ ODM_SEC_WEP104 = 5,\r
+ ODM_WEP_WPA_MIXED = 6, // WEP + WPA\r
+ ODM_SEC_SMS4 = 7,\r
+}ODM_SECURITY_E;\r
+\r
+// ODM_CMNINFO_BW\r
+typedef enum tag_Bandwidth_Definition\r
+{ \r
+ ODM_BW20M = 0,\r
+ ODM_BW40M = 1,\r
+ ODM_BW80M = 2,\r
+ ODM_BW160M = 3,\r
+ ODM_BW5M = 4,\r
+ ODM_BW10M = 5,\r
+ ODM_BW_MAX = 6\r
+}ODM_BW_E;\r
+\r
+// ODM_CMNINFO_CHNL\r
+\r
+// ODM_CMNINFO_BOARD_TYPE\r
+typedef enum tag_Board_Definition\r
+{\r
+ ODM_BOARD_DEFAULT = 0, // The DEFAULT case.\r
+ ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card.\r
+ ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card\r
+ ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT\r
+ ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA\r
+ ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA\r
+ ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW\r
+ ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA\r
+ ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA\r
+}ODM_BOARD_TYPE_E;\r
+\r
+typedef enum tag_ODM_Package_Definition\r
+{\r
+ ODM_PACKAGE_DEFAULT = 0, \r
+ ODM_PACKAGE_QFN68 = BIT(0), \r
+ ODM_PACKAGE_TFBGA90 = BIT(1), \r
+ ODM_PACKAGE_TFBGA79 = BIT(2), \r
+}ODM_Package_TYPE_E;\r
+\r
+typedef enum tag_ODM_TYPE_GPA_Definition {\r
+ TYPE_GPA0 = 0x0000,\r
+ TYPE_GPA1 = 0x0055,\r
+ TYPE_GPA2 = 0x00AA,\r
+ TYPE_GPA3 = 0x00FF,\r
+ TYPE_GPA4 = 0x5500,\r
+ TYPE_GPA5 = 0x5555,\r
+ TYPE_GPA6 = 0x55AA,\r
+ TYPE_GPA7 = 0x55FF,\r
+ TYPE_GPA8 = 0xAA00,\r
+ TYPE_GPA9 = 0xAA55,\r
+ TYPE_GPA10 = 0xAAAA,\r
+ TYPE_GPA11 = 0xAAFF,\r
+ TYPE_GPA12 = 0xFF00,\r
+ TYPE_GPA13 = 0xFF55,\r
+ TYPE_GPA14 = 0xFFAA,\r
+ TYPE_GPA15 = 0xFFFF,\r
+}ODM_TYPE_GPA_E;\r
+\r
+typedef enum tag_ODM_TYPE_APA_Definition {\r
+ TYPE_APA0 = 0x0000,\r
+ TYPE_APA1 = 0x0055,\r
+ TYPE_APA2 = 0x00AA,\r
+ TYPE_APA3 = 0x00FF,\r
+ TYPE_APA4 = 0x5500,\r
+ TYPE_APA5 = 0x5555,\r
+ TYPE_APA6 = 0x55AA,\r
+ TYPE_APA7 = 0x55FF,\r
+ TYPE_APA8 = 0xAA00,\r
+ TYPE_APA9 = 0xAA55,\r
+ TYPE_APA10 = 0xAAAA,\r
+ TYPE_APA11 = 0xAAFF,\r
+ TYPE_APA12 = 0xFF00,\r
+ TYPE_APA13 = 0xFF55,\r
+ TYPE_APA14 = 0xFFAA,\r
+ TYPE_APA15 = 0xFFFF,\r
+}ODM_TYPE_APA_E;\r
+\r
+typedef enum tag_ODM_TYPE_GLNA_Definition {\r
+ TYPE_GLNA0 = 0x0000,\r
+ TYPE_GLNA1 = 0x0055,\r
+ TYPE_GLNA2 = 0x00AA,\r
+ TYPE_GLNA3 = 0x00FF,\r
+ TYPE_GLNA4 = 0x5500,\r
+ TYPE_GLNA5 = 0x5555,\r
+ TYPE_GLNA6 = 0x55AA,\r
+ TYPE_GLNA7 = 0x55FF,\r
+ TYPE_GLNA8 = 0xAA00,\r
+ TYPE_GLNA9 = 0xAA55,\r
+ TYPE_GLNA10 = 0xAAAA,\r
+ TYPE_GLNA11 = 0xAAFF,\r
+ TYPE_GLNA12 = 0xFF00,\r
+ TYPE_GLNA13 = 0xFF55,\r
+ TYPE_GLNA14 = 0xFFAA,\r
+ TYPE_GLNA15 = 0xFFFF,\r
+}ODM_TYPE_GLNA_E;\r
+\r
+typedef enum tag_ODM_TYPE_ALNA_Definition {\r
+ TYPE_ALNA0 = 0x0000,\r
+ TYPE_ALNA1 = 0x0055,\r
+ TYPE_ALNA2 = 0x00AA,\r
+ TYPE_ALNA3 = 0x00FF,\r
+ TYPE_ALNA4 = 0x5500,\r
+ TYPE_ALNA5 = 0x5555,\r
+ TYPE_ALNA6 = 0x55AA,\r
+ TYPE_ALNA7 = 0x55FF,\r
+ TYPE_ALNA8 = 0xAA00,\r
+ TYPE_ALNA9 = 0xAA55,\r
+ TYPE_ALNA10 = 0xAAAA,\r
+ TYPE_ALNA11 = 0xAAFF,\r
+ TYPE_ALNA12 = 0xFF00,\r
+ TYPE_ALNA13 = 0xFF55,\r
+ TYPE_ALNA14 = 0xFFAA,\r
+ TYPE_ALNA15 = 0xFFFF,\r
+}ODM_TYPE_ALNA_E;\r
+\r
+\r
+typedef enum _ODM_RF_RADIO_PATH {\r
+ ODM_RF_PATH_A = 0, //Radio Path A\r
+ ODM_RF_PATH_B = 1, //Radio Path B\r
+ ODM_RF_PATH_C = 2, //Radio Path C\r
+ ODM_RF_PATH_D = 3, //Radio Path D\r
+ ODM_RF_PATH_AB,\r
+ ODM_RF_PATH_AC,\r
+ ODM_RF_PATH_AD,\r
+ ODM_RF_PATH_BC,\r
+ ODM_RF_PATH_BD,\r
+ ODM_RF_PATH_CD,\r
+ ODM_RF_PATH_ABC,\r
+ ODM_RF_PATH_ACD,\r
+ ODM_RF_PATH_BCD,\r
+ ODM_RF_PATH_ABCD,\r
+ // ODM_RF_PATH_MAX, //Max RF number 90 support\r
+} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;\r
+\r
+typedef enum _ODM_PARAMETER_INIT {\r
+ ODM_PRE_SETTING = 0,\r
+ ODM_POST_SETTING = 1,\r
+} ODM_PARAMETER_INIT_E;\r
+\r
+#endif\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff