--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+//============================================================\r
+// include files\r
+//============================================================\r
+#include "mp_precomp.h"\r
+#include "phydm_precomp.h"\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
+#if WPP_SOFTWARE_TRACE\r
+#include "PhyDM_Adaptivity.tmh"\r
+#endif\r
+#endif\r
+\r
+\r
+VOID\r
+Phydm_CheckAdaptivity(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+ \r
+ if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) {\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH));\r
+ } else\r
+#endif\r
+ {\r
+ if (Adaptivity->DynamicLinkAdaptivity == TRUE) {\r
+ if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) {\r
+ Phydm_NHMCounterStatistics(pDM_Odm);\r
+ Phydm_CheckEnvironment(pDM_Odm);\r
+ } else if (!pDM_Odm->bLinked)\r
+ Adaptivity->bCheck = FALSE;\r
+ } else {\r
+ pDM_Odm->Adaptivity_enable = TRUE;\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ else\r
+ pDM_Odm->adaptivity_flag = TRUE;\r
+ }\r
+ }\r
+ } else {\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ }\r
+\r
+ \r
+\r
+}\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+BOOLEAN\r
+Phydm_CheckChannelPlan(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);\r
+ \r
+ if (pMgntInfo->RegEnableAdaptivity == 2) {\r
+ if (pDM_Odm->Carrier_Sense_enable == FALSE) { /*check domain Code for Adaptivity or CarrierSense*/\r
+ if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&\r
+ !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ return TRUE;\r
+ } else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
+ !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ return TRUE;\r
+\r
+ } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ return TRUE;\r
+ }\r
+ } else {\r
+ if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&\r
+ !(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ return TRUE;\r
+ }\r
+\r
+ else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
+ !(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ return TRUE;\r
+\r
+ } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ return TRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ return FALSE;\r
+\r
+}\r
+#endif\r
+\r
+VOID\r
+Phydm_NHMCounterStatisticsInit(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
+ /*PHY parameters initialize for n series*/\r
+ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/\r
+ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/\r
+ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/\r
+ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ /*PHY parameters initialize for ac series*/\r
+ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/\r
+ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/\r
+ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/\r
+ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/\r
+\r
+ }\r
+#endif\r
+}\r
+\r
+VOID\r
+Phydm_NHMCounterStatistics(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))\r
+ return;\r
+\r
+ /*Get NHM report*/\r
+ Phydm_GetNHMCounterStatistics(pDM_Odm);\r
+\r
+ /*Reset NHM counter*/\r
+ Phydm_NHMCounterStatisticsReset(pDM_Odm);\r
+}\r
+\r
+VOID\r
+Phydm_GetNHMCounterStatistics(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u4Byte value32 = 0;\r
+#if (RTL8195A_SUPPORT == 0)\r
+ if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
+ value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
+#endif\r
+ value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);\r
+\r
+ pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);\r
+ pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8);\r
+\r
+}\r
+\r
+VOID\r
+Phydm_NHMCounterStatisticsReset(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);\r
+ }\r
+\r
+#endif\r
+\r
+}\r
+\r
+VOID\r
+Phydm_SetEDCCAThreshold(\r
+ IN PVOID pDM_VOID,\r
+ IN s1Byte H2L,\r
+ IN s1Byte L2H\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)L2H|(u1Byte)H2L<<16));\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)L2H|(u1Byte)H2L<<8));\r
+#endif\r
+\r
+}\r
+\r
+VOID\r
+Phydm_SetLNA(\r
+ IN PVOID pDM_VOID,\r
+ IN PhyDM_set_LNA type\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ \r
+ if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E)) {\r
+ if (type == PhyDM_disable_LNA) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
+ if (pDM_Odm->RFType > ODM_1T1R) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);\r
+ }\r
+ } else if (type == PhyDM_enable_LNA) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
+ if (pDM_Odm->RFType > ODM_1T1R) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);\r
+ }\r
+ }\r
+ } else if (pDM_Odm->SupportICType & ODM_RTL8723B) {\r
+ if (type == PhyDM_disable_LNA) {\r
+ /*S0*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
+ /*S1*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);\r
+ } else if (type == PhyDM_enable_LNA) {\r
+ /*S0*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
+ /*S1*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);\r
+ }\r
+ \r
+ } else if (pDM_Odm->SupportICType & ODM_RTL8812) {\r
+ if (type == PhyDM_disable_LNA) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
+ if (pDM_Odm->RFType > ODM_1T1R) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);\r
+ }\r
+ } else if (type == PhyDM_enable_LNA) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
+ if (pDM_Odm->RFType > ODM_1T1R) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);\r
+ }\r
+ }\r
+ } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) {\r
+ if (type == PhyDM_disable_LNA) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
+ } else if (type == PhyDM_enable_LNA) {\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); \r
+ }\r
+ }\r
+}\r
+\r
+\r
+\r
+VOID\r
+Phydm_SetTRxMux(\r
+ IN PVOID pDM_VOID,\r
+ IN PhyDM_Trx_MUX_Type txMode,\r
+ IN PhyDM_Trx_MUX_Type rxMode\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/\r
+ if (pDM_Odm->RFType > ODM_1T1R) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/\r
+ }\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/\r
+ if (pDM_Odm->RFType > ODM_1T1R) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/\r
+ }\r
+ }\r
+#endif\r
+\r
+}\r
+\r
+VOID\r
+Phydm_MACEDCCAState(\r
+ IN PVOID pDM_VOID,\r
+ IN PhyDM_MACEDCCA_Type State\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ if (State == PhyDM_IGNORE_EDCCA) {\r
+ ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); /*ignore EDCCA reg520[15]=1*/\r
+ ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); /*reg524[11]=0*/\r
+ } else { /*don't set MAC ignore EDCCA signal*/\r
+ ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0\14*/\r
+ ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); /*reg524[11]=1 */\r
+ }\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State));\r
+\r
+}\r
+\r
+BOOLEAN\r
+Phydm_CalNHMcnt(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u2Byte Base = 0;\r
+\r
+ Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;\r
+\r
+ if (Base != 0) {\r
+ pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;\r
+ pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;\r
+ }\r
+ if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)\r
+ return TRUE; /*clean environment*/\r
+ else\r
+ return FALSE; /*noisy environment*/\r
+\r
+}\r
+\r
+\r
+VOID\r
+Phydm_CheckEnvironment(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+ BOOLEAN isCleanEnvironment = FALSE;\r
+\r
+ if (Adaptivity->bFirstLink == TRUE) {\r
+ if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ else\r
+ pDM_Odm->adaptivity_flag = TRUE;\r
+\r
+ Adaptivity->bFirstLink = FALSE;\r
+ return;\r
+ } else {\r
+ if (Adaptivity->NHMWait < 3) { /*Start enter NHM after 4 NHMWait*/\r
+ Adaptivity->NHMWait++;\r
+ Phydm_NHMCounterStatistics(pDM_Odm);\r
+ return;\r
+ } else {\r
+ Phydm_NHMCounterStatistics(pDM_Odm);\r
+ isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);\r
+ if (isCleanEnvironment == TRUE) {\r
+ pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup; /*adaptivity mode*/\r
+ pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;\r
+\r
+ pDM_Odm->Adaptivity_enable = TRUE;\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ else\r
+ pDM_Odm->adaptivity_flag = TRUE;\r
+ } else {\r
+ pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; /*mode2*/\r
+ pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;\r
+\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ }\r
+ Adaptivity->NHMWait = 0;\r
+ Adaptivity->bFirstLink = TRUE;\r
+ Adaptivity->bCheck = TRUE;\r
+ }\r
+\r
+ }\r
+\r
+\r
+}\r
+\r
+VOID\r
+Phydm_SearchPwdBLowerBound(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+ u4Byte value32 = 0;\r
+ u1Byte cnt, IGI = 0x45; /*IGI = 0x50 for cal EDCCA lower bound*/\r
+ u1Byte txEdcca1 = 0, txEdcca0 = 0;\r
+ BOOLEAN bAdjust = TRUE;\r
+ s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;\r
+ s1Byte Diff;\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))\r
+ Phydm_SetLNA(pDM_Odm, PhyDM_disable_LNA);\r
+ else {\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
+ odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);\r
+ }\r
+\r
+ Diff = IGI_target - (s1Byte)IGI;\r
+ TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
+ if (TH_L2H_dmc > 10)\r
+ TH_L2H_dmc = 10;\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
+ ODM_delay_ms(5);\r
+\r
+ while (bAdjust) {\r
+ for (cnt = 0; cnt < 20; cnt++) {\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
+ value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
+ value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord);\r
+#endif\r
+ if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8723B | ODM_RTL8188E)))\r
+ txEdcca1 = txEdcca1 + 1;\r
+ else if (value32 & BIT29)\r
+ txEdcca1 = txEdcca1 + 1;\r
+ else\r
+ txEdcca0 = txEdcca0 + 1;\r
+ }\r
+\r
+ if (txEdcca1 > 1) {\r
+ IGI = IGI - 1;\r
+ TH_L2H_dmc = TH_L2H_dmc + 1;\r
+ if (TH_L2H_dmc > 10)\r
+ TH_L2H_dmc = 10;\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
+ if (TH_L2H_dmc == 10) {\r
+ bAdjust = FALSE;\r
+ Adaptivity->H2L_lb = TH_H2L_dmc;\r
+ Adaptivity->L2H_lb = TH_L2H_dmc;\r
+ pDM_Odm->Adaptivity_IGI_upper = IGI;\r
+ }\r
+\r
+ txEdcca1 = 0;\r
+ txEdcca0 = 0;\r
+\r
+ } else {\r
+ bAdjust = FALSE;\r
+ Adaptivity->H2L_lb = TH_H2L_dmc;\r
+ Adaptivity->L2H_lb = TH_L2H_dmc;\r
+ pDM_Odm->Adaptivity_IGI_upper = IGI;\r
+ txEdcca1 = 0;\r
+ txEdcca0 = 0;\r
+ }\r
+ }\r
+\r
+ pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff;\r
+ Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff;\r
+ Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff;\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))\r
+ Phydm_SetLNA(pDM_Odm, PhyDM_enable_LNA);\r
+ else {\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
+ odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);\r
+ }\r
+ \r
+ Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); /*resume to no link state*/\r
+}\r
+\r
+VOID\r
+Phydm_AdaptivityInit(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+ s1Byte IGItarget = 0x32;\r
+ /*pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;*/\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);\r
+ pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;\r
+ pDM_Odm->DCbackoff = (u1Byte)pMgntInfo->RegDCbackoff;\r
+ Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity;\r
+ Adaptivity->APNumTH = (u1Byte)pMgntInfo->RegAPNumTH;\r
+#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+ pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE;\r
+ pDM_Odm->DCbackoff = pDM_Odm->Adapter->registrypriv.adaptivity_dc_backoff;\r
+ Adaptivity->DynamicLinkAdaptivity = (pDM_Odm->Adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE;\r
+#endif\r
+\r
+\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
+\r
+ if (pDM_Odm->Carrier_Sense_enable == FALSE) {\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ if (pMgntInfo->RegL2HForAdaptivity != 0)\r
+ pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;\r
+ else\r
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+ if (pDM_Odm->Adapter->registrypriv.adaptivity_th_l2h_ini != 0)\r
+ pDM_Odm->TH_L2H_ini = pDM_Odm->Adapter->registrypriv.adaptivity_th_l2h_ini;\r
+ else\r
+#endif\r
+ pDM_Odm->TH_L2H_ini = 0xf5;\r
+ } else\r
+ pDM_Odm->TH_L2H_ini = 0xa;\r
+\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ if (pMgntInfo->RegHLDiffForAdaptivity != 0)\r
+ pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity;\r
+ else\r
+#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+ if (pDM_Odm->Adapter->registrypriv.adaptivity_th_edcca_hl_diff != 0)\r
+ pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->Adapter->registrypriv.adaptivity_th_edcca_hl_diff;\r
+ else\r
+#endif\r
+ pDM_Odm->TH_EDCCA_HL_diff = 7;\r
+\r
+ Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;\r
+ Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;\r
+\r
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
+ prtl8192cd_priv priv = pDM_Odm->priv;\r
+\r
+ if (pDM_Odm->Carrier_Sense_enable) {\r
+ pDM_Odm->TH_L2H_ini = 0xa;\r
+ pDM_Odm->TH_EDCCA_HL_diff = 7;\r
+ } else {\r
+ Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini; /*set by mib*/\r
+ pDM_Odm->TH_EDCCA_HL_diff = 7;\r
+ }\r
+\r
+ Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;\r
+ if (priv->pshare->rf_ft_var.adaptivity_enable == 2)\r
+ Adaptivity->DynamicLinkAdaptivity = TRUE;\r
+ else\r
+ Adaptivity->DynamicLinkAdaptivity = FALSE;\r
+\r
+#endif\r
+\r
+ pDM_Odm->Adaptivity_IGI_upper = 0;\r
+ pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/\r
+\r
+ if (pDM_Odm->bWIFITest == TRUE || pDM_Odm->mp_mode == TRUE)\r
+ pDM_Odm->EDCCA_enable = FALSE;\r
+ else\r
+ pDM_Odm->EDCCA_enable = TRUE; /*even no adaptivity, we still enable EDCCA*/\r
+\r
+ pDM_Odm->TH_L2H_ini_mode2 = 20;\r
+ pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;\r
+ \r
+ Adaptivity->IGI_Base = 0x32;\r
+ Adaptivity->IGI_target = 0x1c;\r
+ Adaptivity->H2L_lb = 0;\r
+ Adaptivity->L2H_lb = 0;\r
+ Adaptivity->NHMWait = 0;\r
+ Adaptivity->bCheck = FALSE;\r
+ Adaptivity->bFirstLink = TRUE;\r
+ Adaptivity->AdajustIGILevel = 0;\r
+\r
+ Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
+\r
+ /*Search pwdB lower bound*/\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);\r
+#endif\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_GAIN_IDX_EDCCA) {\r
+ /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ if (pDM_Odm->SupportICType & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/\r
+ /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
+ }\r
+\r
+ if(!(pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)))\r
+ Phydm_SearchPwdBLowerBound(pDM_Odm);\r
+#endif\r
+\r
+/*we need to consider PwdB upper bound for 8814 later IC*/\r
+ Adaptivity->AdajustIGILevel = (u1Byte)((pDM_Odm->TH_L2H_ini + IGItarget) - PwdBUpperBound + DFIRloss); /*IGI = L2H - PwdB - DFIRloss*/\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x, Adaptivity->AdajustIGILevel = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, Adaptivity->AdajustIGILevel));\r
+\r
+ /*phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue);*/\r
+\r
+}\r
+\r
+\r
+VOID\r
+Phydm_Adaptivity(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte IGI\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ s1Byte TH_L2H_dmc, TH_H2L_dmc;\r
+ s1Byte Diff = 0, IGI_target;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ BOOLEAN bFwCurrentInPSMode = FALSE;\r
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);\r
+\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));\r
+\r
+ /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/\r
+ if (bFwCurrentInPSMode)\r
+ return;\r
+#endif\r
+\r
+ if ((pDM_Odm->EDCCA_enable == FALSE) || (pDM_Odm->bWIFITest == TRUE)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n"));\r
+ return;\r
+ }\r
+\r
+ if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n"));\r
+ pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;\r
+ pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;\r
+ }\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ else{\r
+ if (Phydm_CheckChannelPlan(pDM_Odm) || (pDM_Odm->APTotalNum > Adaptivity->APNumTH)) {\r
+ pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;\r
+ pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;\r
+ }\r
+ }\r
+#endif\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",\r
+ Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));\r
+#if (RTL8195A_SUPPORT == 0)\r
+ if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ /*fix AC series when enable EDCCA hang issue*/\r
+ ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/\r
+ ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/\r
+ }\r
+#endif\r
+ if (*pDM_Odm->pBandWidth == ODM_BW20M) /*CHANNEL_WIDTH_20*/\r
+ IGI_target = Adaptivity->IGI_Base;\r
+ else if (*pDM_Odm->pBandWidth == ODM_BW40M)\r
+ IGI_target = Adaptivity->IGI_Base + 2;\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (*pDM_Odm->pBandWidth == ODM_BW80M)\r
+ IGI_target = Adaptivity->IGI_Base + 2;\r
+#endif\r
+ else\r
+ IGI_target = Adaptivity->IGI_Base;\r
+ Adaptivity->IGI_target = (u1Byte) IGI_target;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d\n",\r
+ (*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity));\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, Adaptivity->AdajustIGILevel= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",\r
+ pDM_Odm->RSSI_Min, Adaptivity->AdajustIGILevel, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));\r
+\r
+ if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));\r
+ return;\r
+ }\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {\r
+ if ((Adaptivity->AdajustIGILevel > IGI) && (pDM_Odm->Adaptivity_enable == TRUE)) \r
+ Diff = Adaptivity->AdajustIGILevel - IGI;\r
+ \r
+ TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else {\r
+ Diff = IGI_target - (s1Byte)IGI;\r
+ TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
+ if (TH_L2H_dmc > 10 && (pDM_Odm->Adaptivity_enable == TRUE))\r
+ TH_L2H_dmc = 10;\r
+\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+\r
+ /*replace lower bound to prevent EDCCA always equal 1*/\r
+ if (TH_H2L_dmc < Adaptivity->H2L_lb)\r
+ TH_H2L_dmc = Adaptivity->H2L_lb;\r
+ if (TH_L2H_dmc < Adaptivity->L2H_lb)\r
+ TH_L2H_dmc = Adaptivity->L2H_lb;\r
+ }\r
+#endif\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));\r
+\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
+ return;\r
+}\r
+\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+\r
+VOID\r
+Phydm_AdaptivityBSOD(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);\r
+ u1Byte count = 0;\r
+ u4Byte u4Value;\r
+\r
+ /*\r
+ 1. turn off RF (TRX Mux in standby mode)\r
+ 2. H2C mac id drop\r
+ 3. ignore EDCCA\r
+ 4. wait for clear FIFO\r
+ 5. don't ignore EDCCA\r
+ 6. turn on RF (TRX Mux in TRx mdoe)\r
+ 7. H2C mac id resume\r
+ */\r
+\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));\r
+\r
+ pAdapter->dropPktByMacIdCnt++;\r
+ pMgntInfo->bDropPktInProgress = TRUE;\r
+\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));\r
+\r
+#if 1\r
+\r
+ /*Standby mode*/\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
+ ODM_Write_DIG(pDM_Odm, 0x20);\r
+\r
+ /*H2C mac id drop*/\r
+ MacIdIndicateDisconnect(pAdapter);\r
+\r
+ /*Ignore EDCCA*/\r
+ Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
+\r
+ delay_ms(50);\r
+ count = 5;\r
+\r
+#else\r
+\r
+ do {\r
+\r
+ u8Byte diffTime, curTime, oldestTime;\r
+ u1Byte queueIdx\r
+\r
+ //3 Standby mode\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
+ ODM_Write_DIG(pDM_Odm, 0x20);\r
+\r
+ //3 H2C mac id drop\r
+ MacIdIndicateDisconnect(pAdapter);\r
+\r
+ //3 Ignore EDCCA\r
+ Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
+\r
+ count++;\r
+ delay_ms(10);\r
+\r
+ // Check latest packet\r
+ curTime = PlatformGetCurrentTime();\r
+ oldestTime = 0xFFFFFFFFFFFFFFFF;\r
+\r
+ for (queueIdx = 0; queueIdx < MAX_TX_QUEUE; queueIdx++) {\r
+ if (!IS_DATA_QUEUE(queueIdx))\r
+ continue;\r
+\r
+ if (!pAdapter->bTcbBusyQEmpty[queueIdx]) {\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("oldestTime = %llu\n", oldestTime));\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("Q[%d] = %llu\n", queueIdx, pAdapter->firstTcbSysTime[queueIdx]));\r
+ if (pAdapter->firstTcbSysTime[queueIdx] < oldestTime)\r
+ oldestTime = pAdapter->firstTcbSysTime[queueIdx];\r
+ }\r
+ }\r
+\r
+ diffTime = curTime - oldestTime;\r
+\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("diff s = %llu\n", (diffTime / 1000000)));\r
+\r
+ } while (((diffTime / 1000000) >= 4) && (oldestTime != 0xFFFFFFFFFFFFFFFF));\r
+#endif\r
+\r
+ /*Resume EDCCA*/\r
+ Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
+\r
+ /*Turn on TRx mode*/\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
+ ODM_Write_DIG(pDM_Odm, 0x20);\r
+\r
+ /*Resume H2C macid*/\r
+ MacIdRecoverMediaStatus(pAdapter);\r
+\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));\r
+\r
+ pMgntInfo->bDropPktInProgress = FALSE;\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));\r
+\r
+}\r
+\r
+#endif\r
+\r
+VOID\r
+phydm_setEDCCAThresholdAPI(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte IGI\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+ s1Byte TH_L2H_dmc, TH_H2L_dmc;\r
+ s1Byte Diff = 0, IGI_target = 0x32;\r
+\r
+ if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {\r
+ if (Adaptivity->AdajustIGILevel > IGI) \r
+ Diff = Adaptivity->AdajustIGILevel - IGI;\r
+ \r
+ TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else {\r
+ Diff = IGI_target - (s1Byte)IGI;\r
+ TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
+ if (TH_L2H_dmc > 10)\r
+ TH_L2H_dmc = 10;\r
+\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+\r
+ /*replace lower bound to prevent EDCCA always equal 1*/\r
+ if (TH_H2L_dmc < Adaptivity->H2L_lb)\r
+ TH_H2L_dmc = Adaptivity->H2L_lb;\r
+ if (TH_L2H_dmc < Adaptivity->L2H_lb)\r
+ TH_L2H_dmc = Adaptivity->L2H_lb;\r
+ }\r
+#endif\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));\r
+\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
+ }\r
+\r
+}\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff