--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+#define _HAL_MP_C_\r
+#ifdef CONFIG_MP_INCLUDED\r
+\r
+#ifdef CONFIG_RTL8188E\r
+#include <rtl8188e_hal.h>\r
+#endif\r
+#ifdef CONFIG_RTL8723B\r
+#include <rtl8723b_hal.h>\r
+#endif\r
+#ifdef CONFIG_RTL8192E\r
+#include <rtl8192e_hal.h>\r
+#endif\r
+#ifdef CONFIG_RTL8814A\r
+#include <rtl8814a_hal.h>\r
+#endif\r
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\r
+#include <rtl8812a_hal.h>\r
+#endif\r
+#ifdef CONFIG_RTL8703B\r
+#include <rtl8703b_hal.h>\r
+#endif\r
+#ifdef CONFIG_RTL8188F\r
+#include <rtl8188f_hal.h>\r
+#endif\r
+\r
+\r
+u8 MgntQuery_NssTxRate(u16 Rate)\r
+{\r
+ u8 NssNum = RF_TX_NUM_NONIMPLEMENT;\r
+ \r
+ if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) || \r
+ (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))\r
+ NssNum = RF_2TX;\r
+ else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) || \r
+ (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))\r
+ NssNum = RF_3TX;\r
+ else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) || \r
+ (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))\r
+ NssNum = RF_4TX;\r
+ else\r
+ NssNum = RF_1TX;\r
+ \r
+ return NssNum;\r
+}\r
+\r
+void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ u8 ChannelToSw = pMptCtx->MptChannelToSw;\r
+ ULONG ulRateIdx = pMptCtx->MptRateIndex;\r
+ ULONG ulbandwidth = pMptCtx->MptBandWidth;\r
+ \r
+ /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/\r
+ if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&\r
+ (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {\r
+ pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);\r
+ pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);\r
+ \r
+ if ((PlatformEFIORead4Byte(pAdapter, 0xF4)&BIT29) == BIT29) {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB);\r
+ } else {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);\r
+ }\r
+ } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/\r
+ \r
+ if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/\r
+ } else {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/\r
+ }\r
+ \r
+ } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);\r
+ }\r
+}\r
+\r
+s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\r
+ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);\r
+\r
+\r
+ if (!netif_running(padapter->pnetdev)) {\r
+ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));\r
+ return _FAIL;\r
+ }\r
+\r
+ if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
+ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));\r
+ return _FAIL;\r
+ }\r
+ if (enable)\r
+ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; \r
+ else\r
+ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;\r
+\r
+ return _SUCCESS;\r
+}\r
+\r
+void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\r
+ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);\r
+\r
+\r
+ *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;\r
+}\r
+\r
+\r
+void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)\r
+{\r
+ u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;\r
+ u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;\r
+ u8 i;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
+ \r
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);\r
+ u1Byte u1Channel = pHalData->CurrentChannel;\r
+ ULONG ulRateIdx = pMptCtx->MptRateIndex;\r
+ u1Byte DataRate = 0xFF;\r
+\r
+ /* Suggested by BB David. 2015.04.27*/
+ if(IS_HARDWARE_TYPE_8188F(Adapter))
+ return;
+
+ DataRate = MptToMgntRate(ulRateIdx);\r
+ \r
+ if (u1Channel == 14 && IS_CCK_RATE(DataRate))\r
+ pHalData->bCCKinCH14 = TRUE;\r
+ else\r
+ pHalData->bCCKinCH14 = FALSE; \r
+\r
+ if (IS_HARDWARE_TYPE_8703B(Adapter)) {\r
+ if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {\r
+ /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */ \r
+ PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);\r
+ PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);\r
+\r
+ RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B CCK in Channel %u\n", u1Channel));\r
+ } else {\r
+ /* Normal setting for 8703B, just recover to the default setting. */\r
+ /* This hardcore values reference from the parameter which BB team gave. */\r
+ for (i = 0 ; i < 2 ; ++i)\r
+ PHY_SetBBReg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);\r
+\r
+ RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B in Channel %u restore to default setting\n", u1Channel));\r
+ }\r
+ } else {\r
+\r
+ /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/\r
+ CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);\r
+\r
+ if (!pHalData->bCCKinCH14) {\r
+ /* Readback the current bb cck swing value and compare with the table to */\r
+ /* get the current swing index */\r
+ for (i = 0; i < CCK_TABLE_SIZE; i++) {\r
+ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&\r
+ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {\r
+ CCKSwingIndex = i;\r
+ RT_TRACE(_module_mp_, DBG_LOUD, ("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
+ (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
+ break;\r
+ }\r
+ }\r
+\r
+ /*Write 0xa22 0xa23*/\r
+ TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +\r
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8);\r
+\r
+\r
+ /*Write 0xa24 ~ 0xa27*/\r
+ TempVal2 = 0;\r
+ TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +\r
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +\r
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16) +\r
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);\r
+\r
+ /*Write 0xa28 0xa29*/\r
+ TempVal3 = 0;\r
+ TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +\r
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8);\r
+ } else {\r
+ for (i = 0; i < CCK_TABLE_SIZE; i++) {\r
+ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&\r
+ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) {\r
+ CCKSwingIndex = i;\r
+ RT_TRACE(_module_mp_, DBG_LOUD, ("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
+ (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
+ break;\r
+ }\r
+ }\r
+\r
+ /*Write 0xa22 0xa23*/\r
+ TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +\r
+ (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8);\r
+\r
+ /*Write 0xa24 ~ 0xa27*/\r
+ TempVal2 = 0;\r
+ TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +\r
+ (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +\r
+ (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16) +\r
+ (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);\r
+\r
+ /*Write 0xa28 0xa29*/\r
+ TempVal3 = 0;\r
+ TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +\r
+ (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8);\r
+ }\r
+\r
+ write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);\r
+ write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);\r
+ write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);\r
+\r
+ }\r
+\r
+}\r
+\r
+void hal_mpt_SetChannel(PADAPTER pAdapter)\r
+{\r
+ u8 eRFPath;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);\r
+ struct mp_priv *pmp = &pAdapter->mppriv;\r
+ u8 channel = pmp->channel;\r
+ u8 bandwidth = pmp->bandwidth;\r
+\r
+ hal_mpt_SwitchRfSetting(pAdapter);\r
+ \r
+ SelectChannel(pAdapter, channel);\r
+ \r
+ pHalData->bSwChnl = _TRUE;\r
+ pHalData->bSetChnlBW = _TRUE;\r
+ rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);\r
+\r
+ hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);\r
+\r
+}\r
+\r
+/*\r
+ * Notice\r
+ * Switch bandwitdth may change center frequency(channel)\r
+ */\r
+void hal_mpt_SetBandwidth(PADAPTER pAdapter)\r
+{\r
+ struct mp_priv *pmp = &pAdapter->mppriv;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ \r
+ u8 channel = pmp->channel;\r
+ u8 bandwidth = pmp->bandwidth;\r
+ \r
+ SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);\r
+ pHalData->bSwChnl = _TRUE;\r
+ pHalData->bSetChnlBW = _TRUE;\r
+ rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);\r
+ \r
+ hal_mpt_SwitchRfSetting(pAdapter);\r
+}\r
+\r
+void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)\r
+{\r
+ RT_TRACE(_module_mp_, DBG_LOUD, ("===>mpt_SetTxPower_Old(): Case = %d\n", Rate));\r
+ switch (Rate) {\r
+ case MPT_CCK:\r
+ {\r
+ u4Byte TxAGC = 0, pwr = 0;\r
+ u1Byte rf;\r
+\r
+ pwr = pTxPower[ODM_RF_PATH_A];\r
+ if (pwr < 0x3f) {\r
+ TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);\r
+ }\r
+ pwr = pTxPower[ODM_RF_PATH_B];\r
+ if (pwr < 0x3f) {\r
+ TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);\r
+ }\r
+ \r
+ } break;\r
+\r
+ case MPT_OFDM_AND_HT:\r
+ {\r
+ u4Byte TxAGC = 0;\r
+ u1Byte pwr = 0, rf;\r
+ \r
+ pwr = pTxPower[0];\r
+ if (pwr < 0x3f) {\r
+ TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
+ DBG_871X("HT Tx-rf(A) Power = 0x%x\n", TxAGC);\r
+ \r
+ PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
+ }\r
+ TxAGC = 0;\r
+ pwr = pTxPower[1];\r
+ if (pwr < 0x3f) {\r
+ TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
+ DBG_871X("HT Tx-rf(B) Power = 0x%x\n", TxAGC);\r
+ \r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
+ PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
+ }\r
+ } break;\r
+\r
+ default:\r
+ break;\r
+ } \r
+ DBG_871X("<===mpt_SetTxPower_Old()\n");\r
+}\r
+\r
+\r
+\r
+void \r
+mpt_SetTxPower(\r
+ PADAPTER pAdapter,\r
+ MPT_TXPWR_DEF Rate,\r
+ pu1Byte pTxPower\r
+ )\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+\r
+ u1Byte path = 0 , i = 0, MaxRate = MGN_6M;\r
+ u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B;\r
+ \r
+ if (IS_HARDWARE_TYPE_8814A(pAdapter))\r
+ EndPath = ODM_RF_PATH_D;\r
+ else if (IS_HARDWARE_TYPE_8188F(pAdapter))
+ EndPath = ODM_RF_PATH_A;
+\r
+ switch (Rate) {\r
+ case MPT_CCK:\r
+ {\r
+ u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};\r
+\r
+ for (path = StartPath; path <= EndPath; path++)\r
+ for (i = 0; i < sizeof(rate); ++i)\r
+ PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); \r
+ }\r
+ break;\r
+ \r
+ case MPT_OFDM:\r
+ {\r
+ u1Byte rate[] = {\r
+ MGN_6M, MGN_9M, MGN_12M, MGN_18M,\r
+ MGN_24M, MGN_36M, MGN_48M, MGN_54M,\r
+ };\r
+\r
+ for (path = StartPath; path <= EndPath; path++)\r
+ for (i = 0; i < sizeof(rate); ++i)\r
+ PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); \r
+ } break;\r
+ \r
+ case MPT_HT:\r
+ {\r
+ u1Byte rate[] = {\r
+ MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,\r
+ MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,\r
+ MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,\r
+ MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,\r
+ MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,\r
+ MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,\r
+ MGN_MCS30, MGN_MCS31,\r
+ };\r
+ if (pHalData->rf_type == RF_3T3R)\r
+ MaxRate = MGN_MCS23;\r
+ else if (pHalData->rf_type == RF_2T2R)\r
+ MaxRate = MGN_MCS15;\r
+ else\r
+ MaxRate = MGN_MCS7;\r
+ \r
+ for (path = StartPath; path <= EndPath; path++) {\r
+ for (i = 0; i < sizeof(rate); ++i) {\r
+ if (rate[i] > MaxRate)\r
+ break; \r
+ PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);\r
+ }\r
+ }\r
+ } break;\r
+ \r
+ case MPT_VHT:\r
+ {\r
+ u1Byte rate[] = {\r
+ MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,\r
+ MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,\r
+ MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,\r
+ MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,\r
+ MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,\r
+ MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,\r
+ MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,\r
+ MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,\r
+ };\r
+ \r
+ if (pHalData->rf_type == RF_3T3R)\r
+ MaxRate = MGN_VHT3SS_MCS9;\r
+ else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)\r
+ MaxRate = MGN_VHT2SS_MCS9;\r
+ else\r
+ MaxRate = MGN_VHT1SS_MCS9;\r
+\r
+ for (path = StartPath; path <= EndPath; path++) {\r
+ for (i = 0; i < sizeof(rate); ++i) {\r
+ if (rate[i] > MaxRate)\r
+ break; \r
+ PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);\r
+ }\r
+ }\r
+ } break;\r
+ \r
+ default:\r
+ DBG_871X("<===mpt_SetTxPower: Illegal channel!!\n");\r
+ break;\r
+ }\r
+\r
+}\r
+\r
+\r
+void hal_mpt_SetTxPower(PADAPTER pAdapter)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;\r
+\r
+ if (pHalData->rf_chip < RF_TYPE_MAX) {\r
+ if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
+ IS_HARDWARE_TYPE_8723B(pAdapter) ||
+ IS_HARDWARE_TYPE_8192E(pAdapter) ||
+ IS_HARDWARE_TYPE_8703B(pAdapter) ||
+ IS_HARDWARE_TYPE_8188F(pAdapter)) {
+ u8 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);\r
+\r
+ DBG_8192C("===> MPT_ProSetTxPower: Old\n");\r
+\r
+ RT_TRACE(_module_mp_, DBG_LOUD, ("===> MPT_ProSetTxPower[Old]:\n"));\r
+ mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel); \r
+ mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);\r
+\r
+ } else {\r
+ DBG_871X("===> MPT_ProSetTxPower: Jaguar\n");\r
+ mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);\r
+ mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);\r
+ mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);\r
+ mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);\r
+\r
+ }\r
+ } else\r
+ DBG_8192C("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);\r
+\r
+ ODM_ClearTxPowerTrackingState(pDM_Odm);\r
+\r
+}\r
+\r
+\r
+void hal_mpt_SetDataRate(PADAPTER pAdapter)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ u32 DataRate;\r
+\r
+ DataRate = MptToMgntRate(pMptCtx->MptRateIndex);\r
+ \r
+ hal_mpt_SwitchRfSetting(pAdapter);\r
+\r
+ hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);\r
+#ifdef CONFIG_RTL8723B\r
+ if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {\r
+ if (IS_CCK_RATE(DataRate)) {\r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_A)\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6); \r
+ else\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);\r
+ } else {\r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_A)\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); \r
+ else\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); \r
+ }\r
+ }\r
+ \r
+ if ((IS_HARDWARE_TYPE_8723BS(pAdapter) && \r
+ ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {\r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_A)\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); \r
+ else\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); \r
+ }\r
+#endif \r
+}\r
+\r
+\r
+#define RF_PATH_AB 22\r
+\r
+#ifdef CONFIG_RTL8814A\r
+VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)\r
+{\r
+ u1Byte Path = 0;\r
+ u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;\r
+\r
+ for (Path; Path <= ODM_RF_PATH_D; Path++) {\r
+ switch (Path) {\r
+ case ODM_RF_PATH_B:\r
+ IGReg = rB_IGI_Jaguar;\r
+ break;\r
+ case ODM_RF_PATH_C:\r
+ IGReg = rC_IGI_Jaguar2;\r
+ break;\r
+ case ODM_RF_PATH_D:\r
+ IGReg = rD_IGI_Jaguar2;\r
+ break;\r
+ default:\r
+ IGReg = rA_IGI_Jaguar;\r
+ break;\r
+ }\r
+\r
+ IGvalue = PHY_QueryBBReg(pAdapter, IGReg, bMaskByte0);\r
+ PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue+2); \r
+ PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue);\r
+ }\r
+}\r
+\r
+VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)\r
+{\r
+\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;\r
+ R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */\r
+ R_ANTENNA_SELECT_CCK *p_cck_txrx;\r
+ u8 ForcedDataRate = MptToMgntRate(pMptCtx->MptRateIndex);\r
+ u8 HtStbcCap = pAdapter->registrypriv.stbc_cap;\r
+ /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/\r
+ /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/\r
+\r
+ u32 ulAntennaTx = pHalData->AntennaTxPath;\r
+ u32 ulAntennaRx = pHalData->AntennaRxPath;\r
+ u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);\r
+\r
+ if (NssforRate == RF_2TX) { \r
+ DBG_871X("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);\r
+\r
+ switch (ulAntennaTx) {\r
+ case ANTENNA_BC:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_BC;\r
+ /*pHalData->ValidTxPath = 0x06; linux no use */\r
+ PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/\r
+ break;\r
+\r
+ case ANTENNA_CD:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_CD;\r
+ /*pHalData->ValidTxPath = 0x0C;*/\r
+ PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/\r
+ break;\r
+ case ANTENNA_AB: default:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_AB;\r
+ /*pHalData->ValidTxPath = 0x03;*/\r
+ PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/\r
+ break;\r
+ }\r
+\r
+ } else if (NssforRate == RF_3TX) {\r
+ DBG_871X("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);\r
+\r
+ switch (ulAntennaTx) {\r
+ case ANTENNA_BCD:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_BCD;\r
+ /*pHalData->ValidTxPath = 0x0e;*/\r
+ PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/\r
+ break;\r
+\r
+ case ANTENNA_ABC: default:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_ABC;\r
+ /*pHalData->ValidTxPath = 0x0d;*/\r
+ PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/\r
+ break;\r
+ }\r
+\r
+ } else { /*/if(NssforRate == RF_1TX)*/\r
+ DBG_871X("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);\r
+ switch (ulAntennaTx) {\r
+ case ANTENNA_B:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_B;\r
+ /*pHalData->ValidTxPath = 0x02;*/\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/\r
+ PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/\r
+ PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/\r
+ break;\r
+\r
+ case ANTENNA_C:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_C;\r
+ /*pHalData->ValidTxPath = 0x04;*/\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/\r
+ PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/\r
+ PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/\r
+ break;\r
+\r
+ case ANTENNA_D:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_D;\r
+ /*pHalData->ValidTxPath = 0x08;*/\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/\r
+ PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/\r
+ PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/\r
+ break;\r
+\r
+ case ANTENNA_A: default:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_A;\r
+ /*pHalData->ValidTxPath = 0x01;*/\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/\r
+ PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/\r
+ PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/\r
+ break;\r
+ }\r
+ }\r
+\r
+ switch (ulAntennaRx) {\r
+ case ANTENNA_A:\r
+ /*pHalData->ValidRxPath = 0x01;*/\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/\r
+ /*/ CCA related PD_delay_th*/\r
+ PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\r
+ PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\r
+ break;\r
+\r
+ case ANTENNA_B:\r
+ /*pHalData->ValidRxPath = 0x02;*/\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); \r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1); \r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/\r
+ /*/ CCA related PD_delay_th*/\r
+ PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\r
+ PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\r
+ break;\r
+\r
+ case ANTENNA_C:\r
+ /*pHalData->ValidRxPath = 0x04;*/\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44); \r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/\r
+ /*/ CCA related PD_delay_th*/\r
+ PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\r
+ PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\r
+ break;\r
+\r
+ case ANTENNA_D:\r
+ /*pHalData->ValidRxPath = 0x08;*/\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88); \r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/\r
+ /*/ CCA related PD_delay_th*/\r
+ PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\r
+ PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\r
+ break;\r
+\r
+ case ANTENNA_BC: \r
+ /*pHalData->ValidRxPath = 0x06;*/\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/\r
+ /*/ CCA related PD_delay_th*/\r
+ PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\r
+ PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\r
+ break;\r
+\r
+ case ANTENNA_CD: \r
+ /*pHalData->ValidRxPath = 0x0C;*/\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/\r
+ /*/ CCA related PD_delay_th*/\r
+ PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\r
+ PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\r
+ break;\r
+\r
+ case ANTENNA_BCD: \r
+ /*pHalData->ValidRxPath = 0x0e;*/\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/\r
+ /*/ CCA related PD_delay_th*/\r
+ PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);\r
+ PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);\r
+ break;\r
+\r
+ case ANTENNA_ABCD: \r
+ /*pHalData->ValidRxPath = 0x0f;*/\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);\r
+ PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/\r
+ /*/ CCA related PD_delay_th*/\r
+ PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);\r
+ PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);\r
+ break;\r
+\r
+ default:\r
+ RT_TRACE(_module_mp_, _drv_warning_, ("Unknown Rx antenna.\n"));\r
+ break;\r
+ }\r
+\r
+ PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);\r
+\r
+ mpt_ToggleIG_8814A(pAdapter);\r
+ RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));\r
+}\r
+\r
+VOID\r
+mpt_SetSingleTone_8814A(\r
+ IN PADAPTER pAdapter,\r
+ IN BOOLEAN bSingleTone,\r
+ IN BOOLEAN bEnPMacTx)\r
+{\r
+\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A;\r
+ static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;\r
+\r
+ if (bSingleTone) { \r
+ regIG0 = PHY_QueryBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/\r
+ regIG1 = PHY_QueryBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/\r
+ regIG2 = PHY_QueryBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/\r
+ regIG3 = PHY_QueryBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/\r
+\r
+ switch (pMptCtx->MptRfPath) {\r
+ case ODM_RF_PATH_A: case ODM_RF_PATH_B:\r
+ case ODM_RF_PATH_C: case ODM_RF_PATH_D:\r
+ StartPath = pMptCtx->MptRfPath;\r
+ EndPath = pMptCtx->MptRfPath;\r
+ break;\r
+ case ODM_RF_PATH_AB:\r
+ EndPath = ODM_RF_PATH_B;\r
+ break;\r
+ case ODM_RF_PATH_BC:\r
+ StartPath = ODM_RF_PATH_B;\r
+ EndPath = ODM_RF_PATH_C;\r
+ break;\r
+ case ODM_RF_PATH_ABC:\r
+ EndPath = ODM_RF_PATH_C;\r
+ break;\r
+ case ODM_RF_PATH_BCD:\r
+ StartPath = ODM_RF_PATH_B;\r
+ EndPath = ODM_RF_PATH_D;\r
+ break;\r
+ case ODM_RF_PATH_ABCD:\r
+ EndPath = ODM_RF_PATH_D;\r
+ break;\r
+ }\r
+\r
+ if (bEnPMacTx == FALSE) {\r
+ hal_mpt_SetOFDMContinuousTx(pAdapter, _TRUE);\r
+ issue_nulldata(pAdapter, NULL, 1, 3, 500);\r
+ }\r
+\r
+ PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/\r
+\r
+ for (StartPath; StartPath <= EndPath; StartPath++) {\r
+ PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */\r
+ PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/\r
+\r
+ PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/\r
+ }\r
+\r
+ PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/\r
+ PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/\r
+ PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/\r
+ PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/\r
+ \r
+ } else {\r
+ \r
+ switch (pMptCtx->MptRfPath) {\r
+ case ODM_RF_PATH_A: case ODM_RF_PATH_B:\r
+ case ODM_RF_PATH_C: case ODM_RF_PATH_D:\r
+ StartPath = pMptCtx->MptRfPath;\r
+ EndPath = pMptCtx->MptRfPath;\r
+ break;\r
+ case ODM_RF_PATH_AB:\r
+ EndPath = ODM_RF_PATH_B;\r
+ break;\r
+ case ODM_RF_PATH_BC:\r
+ StartPath = ODM_RF_PATH_B;\r
+ EndPath = ODM_RF_PATH_C;\r
+ break;\r
+ case ODM_RF_PATH_ABC:\r
+ EndPath = ODM_RF_PATH_C;\r
+ break;\r
+ case ODM_RF_PATH_BCD:\r
+ StartPath = ODM_RF_PATH_B;\r
+ EndPath = ODM_RF_PATH_D;\r
+ break;\r
+ case ODM_RF_PATH_ABCD:\r
+ EndPath = ODM_RF_PATH_D;\r
+ break;\r
+ }\r
+ \r
+ for (StartPath; StartPath <= EndPath; StartPath++)\r
+ PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x0); /*// RF LO disabled*/\r
+\r
+ \r
+ PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/\r
+\r
+ if (bEnPMacTx == FALSE)\r
+ hal_mpt_SetOFDMContinuousTx(pAdapter, _FALSE);\r
+\r
+ PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/\r
+ PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/\r
+ PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/\r
+ PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/\r
+ }\r
+}\r
+\r
+#endif\r
+\r
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\r
+void mpt_SetRFPath_8812A(PADAPTER pAdapter)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;\r
+ u32 ulAntennaTx, ulAntennaRx;\r
+\r
+ ulAntennaTx = pHalData->AntennaTxPath;\r
+ ulAntennaRx = pHalData->AntennaRxPath;\r
+\r
+ switch (ulAntennaTx) {\r
+ case ANTENNA_A:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_A;\r
+ PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);\r
+ if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))\r
+ PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); \r
+ break;\r
+ case ANTENNA_B:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_B;\r
+ PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);\r
+ if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))\r
+ PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);\r
+ break;\r
+ case ANTENNA_AB:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_AB;\r
+ PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);\r
+ if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))\r
+ PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);\r
+ break;\r
+ default:\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_AB;\r
+ DBG_871X("Unknown Tx antenna.\n");\r
+ break;\r
+ }\r
+\r
+ switch (ulAntennaRx) {\r
+ u32 reg0xC50 = 0;\r
+ case ANTENNA_A:\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); \r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); \r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19|BIT18|BIT17|BIT16, 0x3); \r
+\r
+ /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/\r
+ reg0xC50 = PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0);\r
+ PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50+2); \r
+ PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50); \r
+ break;\r
+ case ANTENNA_B:\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19|BIT18|BIT17|BIT16, 0x3); \r
+\r
+ /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/\r
+ reg0xC50 = PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0);\r
+ PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50+2); \r
+ PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50); \r
+ break;\r
+ case ANTENNA_AB:\r
+ PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33); \r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/\r
+ PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); \r
+ break;\r
+ default:\r
+ DBG_871X("Unknown Rx antenna.\n");\r
+ break;\r
+ }\r
+ RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));\r
+}\r
+#endif\r
+\r
+\r
+#ifdef CONFIG_RTL8723B\r
+void mpt_SetRFPath_8723B(PADAPTER pAdapter)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ u32 ulAntennaTx, ulAntennaRx;\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;\r
+ PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
+\r
+ ulAntennaTx = pHalData->AntennaTxPath;\r
+ ulAntennaRx = pHalData->AntennaRxPath;\r
+\r
+ if (pHalData->rf_chip >= RF_TYPE_MAX) {\r
+ DBG_8192C("This RF chip ID is not supported\n");\r
+ return;\r
+ }\r
+\r
+ switch (pAdapter->mppriv.antenna_tx) {\r
+ u8 p = 0, i = 0;\r
+ case ANTENNA_A: /*/ Actually path S1 (Wi-Fi)*/\r
+ {\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_A; \r
+ PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);\r
+ PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/\r
+\r
+ /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/\r
+ if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);\r
+ else\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);\r
+\r
+\r
+ for (i = 0; i < 3; ++i) {\r
+ u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];\r
+ u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];\r
+ \r
+ if (offset != 0) {\r
+ PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
+ DBG_8192C("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);\r
+ }\r
+\r
+ }\r
+ for (i = 0; i < 2; ++i) {\r
+ u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];\r
+ u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];\r
+ \r
+ if (offset != 0) {\r
+ PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); \r
+ DBG_8192C("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
+ }\r
+ }\r
+ }\r
+ break;\r
+ case ANTENNA_B: /*/ Actually path S0 (BT)*/\r
+ {\r
+ u4Byte offset;\r
+ u4Byte data;\r
+ \r
+ pMptCtx->MptRfPath = ODM_RF_PATH_B;\r
+ PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);\r
+ PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/\r
+ \r
+ /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/\r
+ if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);\r
+ else\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);\r
+\r
+ for (i = 0; i < 3; ++i) {\r
+ /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/\r
+ offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];\r
+ data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];\r
+ if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {\r
+ PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
+ DBG_8192C("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
+ }\r
+ }\r
+ /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/\r
+ for (i = 0; i < 2; ++i) {\r
+ offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];\r
+ data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];\r
+ \r
+ if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {\r
+ PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
+ DBG_8192C("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
+ }\r
+ }\r
+ }\r
+ break;\r
+ default:\r
+ pMptCtx->MptRfPath = RF_PATH_AB;\r
+ RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));\r
+ break;\r
+ }\r
+ RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));\r
+}\r
+#endif\r
+\r
+#ifdef CONFIG_RTL8703B\r
+void mpt_SetRFPath_8703B(PADAPTER pAdapter)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ u4Byte ulAntennaTx, ulAntennaRx;\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;\r
+ PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
+\r
+ ulAntennaTx = pHalData->AntennaTxPath;\r
+ ulAntennaRx = pHalData->AntennaRxPath;\r
+\r
+ if (pHalData->rf_chip >= RF_TYPE_MAX) {\r
+ DBG_871X("This RF chip ID is not supported\n");\r
+ return;\r
+ }\r
+\r
+ switch (pAdapter->mppriv.antenna_tx) {\r
+ u1Byte p = 0, i = 0;\r
+\r
+ case ANTENNA_A: /* Actually path S1 (Wi-Fi) */\r
+ {\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_A; \r
+ PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);\r
+ PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/\r
+\r
+ for (i = 0; i < 3; ++i) {\r
+ u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];\r
+ u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];\r
+\r
+ if (offset != 0) {\r
+ PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
+ DBG_871X("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);\r
+ }\r
+\r
+ }\r
+ for (i = 0; i < 2; ++i) {\r
+ u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];\r
+ u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];\r
+\r
+ if (offset != 0) {\r
+ PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); \r
+ DBG_871X("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
+ }\r
+ }\r
+ }\r
+ break;\r
+ case ANTENNA_B: /* Actually path S0 (BT)*/\r
+ {\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_B;\r
+ PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);\r
+ PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */\r
+\r
+ for (i = 0; i < 3; ++i) {\r
+ u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];\r
+ u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];\r
+\r
+ if (pRFCalibrateInfo->TxIQC_8703B[i][0] != 0) {\r
+ PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
+ DBG_871X("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
+ }\r
+ }\r
+ for (i = 0; i < 2; ++i) {\r
+ u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];\r
+ u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];\r
+\r
+ if (pRFCalibrateInfo->RxIQC_8703B[i][0] != 0) {\r
+ PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
+ DBG_871X("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
+ }\r
+ }\r
+ }\r
+ break;\r
+ default:\r
+ pMptCtx->MptRfPath = RF_PATH_AB; \r
+ RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));\r
+ break;\r
+ }\r
+\r
+ RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));\r
+}\r
+#endif\r
+\r
+\r
+VOID mpt_SetRFPath_819X(PADAPTER pAdapter)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ u4Byte ulAntennaTx, ulAntennaRx;\r
+ R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */\r
+ R_ANTENNA_SELECT_CCK *p_cck_txrx;\r
+ u1Byte r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;\r
+ u1Byte chgTx = 0, chgRx = 0;\r
+ u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;\r
+\r
+ ulAntennaTx = pHalData->AntennaTxPath;\r
+ ulAntennaRx = pHalData->AntennaRxPath;\r
+ \r
+ p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;\r
+ p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;\r
+\r
+ p_ofdm_tx->r_ant_ht1 = 0x1;\r
+ p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/\r
+ p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */\r
+\r
+ switch (ulAntennaTx) {\r
+ case ANTENNA_A:\r
+ p_ofdm_tx->r_tx_antenna = 0x1;\r
+ r_ofdm_tx_en_val = 0x1;\r
+ p_ofdm_tx->r_ant_l = 0x1;\r
+ p_ofdm_tx->r_ant_ht_s1 = 0x1;\r
+ p_ofdm_tx->r_ant_non_ht_s1 = 0x1;\r
+ p_cck_txrx->r_ccktx_enable = 0x8;\r
+ chgTx = 1;\r
+ /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/\r
+ /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/\r
+ {\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);\r
+ r_ofdm_tx_en_val = 0x3;\r
+ /*/ Power save*/\r
+ /*/cosa r_ant_select_ofdm_val = 0x11111111;*/\r
+ /*/ We need to close RFB by SW control*/\r
+ if (pHalData->rf_type == RF_2T2R) {\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);\r
+ }\r
+ }\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_A;\r
+ break;\r
+ case ANTENNA_B:\r
+ p_ofdm_tx->r_tx_antenna = 0x2;\r
+ r_ofdm_tx_en_val = 0x2;\r
+ p_ofdm_tx->r_ant_l = 0x2;\r
+ p_ofdm_tx->r_ant_ht_s1 = 0x2;\r
+ p_ofdm_tx->r_ant_non_ht_s1 = 0x2;\r
+ p_cck_txrx->r_ccktx_enable = 0x4;\r
+ chgTx = 1;\r
+ /*/ From SD3 Willis suggestion !!! Set RF A as standby*/\r
+ /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/\r
+ {\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);\r
+\r
+ /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/\r
+ /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/\r
+ if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);\r
+ /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);\r
+ }\r
+ }\r
+ pMptCtx->MptRfPath = ODM_RF_PATH_B; \r
+ break;\r
+ case ANTENNA_AB:/*/ For 8192S*/\r
+ p_ofdm_tx->r_tx_antenna = 0x3;\r
+ r_ofdm_tx_en_val = 0x3;\r
+ p_ofdm_tx->r_ant_l = 0x3;\r
+ p_ofdm_tx->r_ant_ht_s1 = 0x3;\r
+ p_ofdm_tx->r_ant_non_ht_s1 = 0x3;\r
+ p_cck_txrx->r_ccktx_enable = 0xC;\r
+ chgTx = 1;\r
+ /*/ From SD3Willis suggestion !!! Set RF B as standby*/\r
+ /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/\r
+ {\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);\r
+ /* Disable Power save*/ \r
+ /*cosa r_ant_select_ofdm_val = 0x3321333;*/\r
+ /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/\r
+ if (pHalData->rf_type == RF_2T2R) {\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);\r
+\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);\r
+ /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);\r
+ }\r
+ } \r
+ pMptCtx->MptRfPath = ODM_RF_PATH_AB;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ \r
+ \r
+/*// r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D\r
+// r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D\r
+// r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */\r
+ switch (ulAntennaRx) {\r
+ case ANTENNA_A:\r
+ r_rx_antenna_ofdm = 0x1; /* A*/\r
+ p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/\r
+ p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/\r
+ chgRx = 1;\r
+ break;\r
+ case ANTENNA_B:\r
+ r_rx_antenna_ofdm = 0x2; /*/ B*/\r
+ p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/\r
+ p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/\r
+ chgRx = 1;\r
+ break;\r
+ case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/\r
+ r_rx_antenna_ofdm = 0x3;/*/ AB*/\r
+ p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/\r
+ p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/\r
+ chgRx = 1;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+\r
+ if (chgTx && chgRx) {\r
+ switch (pHalData->rf_chip) {\r
+ case RF_8225:\r
+ case RF_8256:\r
+ case RF_6052:\r
+ /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/\r
+ PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/\r
+ PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/\r
+ PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/\r
+ if (IS_HARDWARE_TYPE_8192E(pAdapter)) {\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/\r
+ PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/\r
+ }\r
+ PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/\r
+ break;\r
+\r
+ default:\r
+ DBG_871X("Unsupported RFChipID for switching antenna.\n");\r
+ break;\r
+ }\r
+ }\r
+} /* MPT_ProSetRFPath */\r
+\r
+\r
+void hal_mpt_SetAntenna(PADAPTER pAdapter)\r
+\r
+{\r
+ DBG_871X("Do %s\n", __func__);\r
+#ifdef CONFIG_RTL8814A\r
+ if (IS_HARDWARE_TYPE_8814A(pAdapter)) {\r
+ mpt_SetRFPath_8814A(pAdapter);\r
+ return;\r
+ }\r
+#endif\r
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\r
+ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {\r
+ mpt_SetRFPath_8812A(pAdapter);\r
+ return;\r
+ }\r
+#endif\r
+#ifdef CONFIG_RTL8723B\r
+ if (IS_HARDWARE_TYPE_8723B(pAdapter)) {\r
+ mpt_SetRFPath_8723B(pAdapter);\r
+ return;\r
+ } \r
+#endif \r
+#ifdef CONFIG_RTL8703B\r
+ if (IS_HARDWARE_TYPE_8703B(pAdapter)) {\r
+ mpt_SetRFPath_8703B(pAdapter);\r
+ return;\r
+ } \r
+#endif \r
+\r
+/* else if (IS_HARDWARE_TYPE_8821B(pAdapter))\r
+ mpt_SetRFPath_8821B(pAdapter);\r
+ Prepare for 8822B\r
+ else if (IS_HARDWARE_TYPE_8822B(Context))\r
+ mpt_SetRFPath_8822B(Context);\r
+*/ \r
+ mpt_SetRFPath_819X(pAdapter);\r
+ DBG_871X("mpt_SetRFPath_819X Do %s\n", __func__);\r
+\r
+}\r
+\r
+\r
+s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+\r
+ if (!netif_running(pAdapter->pnetdev)) {\r
+ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));\r
+ return _FAIL;\r
+ }\r
+\r
+\r
+ if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
+ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));\r
+ return _FAIL;\r
+ }\r
+\r
+\r
+ target_ther &= 0xff;\r
+ if (target_ther < 0x07)\r
+ target_ther = 0x07;\r
+ else if (target_ther > 0x1d)\r
+ target_ther = 0x1d;\r
+\r
+ pHalData->EEPROMThermalMeter = target_ther;\r
+\r
+ return _SUCCESS;\r
+}\r
+\r
+\r
+void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)\r
+{\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);\r
+\r
+}\r
+\r
+\r
+u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)\r
+\r
+{\r
+ u32 ThermalValue = 0;\r
+\r
+ ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/\r
+ return (u8)ThermalValue;\r
+\r
+}\r
+\r
+\r
+void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)\r
+{\r
+#if 0\r
+ fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);\r
+ rtw_msleep_os(1000);\r
+ fw_cmd_data(pAdapter, value, 1);\r
+ *value &= 0xFF;\r
+#else\r
+ hal_mpt_TriggerRFThermalMeter(pAdapter);\r
+ rtw_msleep_os(1000);\r
+ *value = hal_mpt_ReadRFThermalMeter(pAdapter);\r
+#endif\r
+\r
+}\r
+\r
+\r
+void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ \r
+ pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;\r
+ \r
+ if (bStart) {/*/ Start Single Carrier.*/\r
+ RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));\r
+ /*/ Start Single Carrier.*/\r
+ /*/ 1. if OFDM block on?*/\r
+ if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
+ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/\r
+\r
+ /*/ 2. set CCK test mode off, set to CCK normal mode*/\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);\r
+\r
+ /*/ 3. turn on scramble setting*/\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);\r
+\r
+ /*/ 4. Turn On Continue Tx and turn off the other test modes.*/\r
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)\r
+ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)\r
+ PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_SingleCarrier);\r
+ else\r
+#endif \r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleCarrier);\r
+\r
+ } else {\r
+ /*/ Stop Single Carrier.*/\r
+ /*/ Stop Single Carrier.*/\r
+ /*/ Turn off all test modes.*/\r
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) \r
+ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)\r
+ PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
+ else\r
+#endif\r
+ \r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
+\r
+ rtw_msleep_os(10);\r
+ /*/BB Reset*/\r
+ PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
+ PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
+ }\r
+}\r
+\r
+\r
+void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ u4Byte ulAntennaTx = pHalData->AntennaTxPath;\r
+ static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;\r
+ u8 rfPath;\r
+\r
+ switch (ulAntennaTx) {\r
+ case ANTENNA_B:\r
+ rfPath = ODM_RF_PATH_B;\r
+ break;\r
+ case ANTENNA_C:\r
+ rfPath = ODM_RF_PATH_C;\r
+ break;\r
+ case ANTENNA_D:\r
+ rfPath = ODM_RF_PATH_D;\r
+ break;\r
+ case ANTENNA_A:\r
+ default: \r
+ rfPath = ODM_RF_PATH_A;\r
+ break;\r
+ }\r
+\r
+ pAdapter->mppriv.MptCtx.bSingleTone = bStart;\r
+ if (bStart) {\r
+ /*/ Start Single Tone.*/\r
+ /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/\r
+ if (IS_HARDWARE_TYPE_8188E(pAdapter)) {\r
+ regRF = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);\r
+ \r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ \r
+ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);\r
+ } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/\r
+ /*/Set MAC REG 88C: Prevent SingleTone Fail*/\r
+ PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0xF);\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO disabled*/\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/\r
+ } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {\r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/\r
+ } else { \r
+ /*/ S0/S1 both use PATH A to configure*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/\r
+ }\r
+ } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {\r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */\r
+ }\r
+ } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {\r
+ /*Set BB REG 88C: Prevent SingleTone Fail*/\r
+ PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1);\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2);\r
+ } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+ u1Byte p = ODM_RF_PATH_A;\r
+ \r
+ regRF = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);\r
+ regBB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);\r
+ regBB1 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);\r
+ regBB2 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord);\r
+ regBB3 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord);\r
+ \r
+ PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x0); /*/ Disable CCK and OFDM*/\r
+ \r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {\r
+ for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { \r
+ PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */\r
+ PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/\r
+ PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/\r
+ }\r
+ } else {\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/\r
+ } \r
+ \r
+ PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/\r
+ PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/\r
+ \r
+ if (pHalData->ExternalPA_5G) {\r
+ PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/\r
+ PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/\r
+ } else if (pHalData->ExternalPA_2G) {\r
+ PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/\r
+ PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/\r
+ }\r
+#endif\r
+ }\r
+#ifdef CONFIG_RTL8814A \r
+ else if (IS_HARDWARE_TYPE_8814A(pAdapter))\r
+ mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);\r
+#endif\r
+ else /*/ Turn On SingleTone and turn off the other test modes.*/\r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleTone); \r
+\r
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
+\r
+ } else {/*/ Stop Single Ton e.*/\r
+\r
+ if (IS_HARDWARE_TYPE_8188E(pAdapter)) {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, regRF);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);\r
+ } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0);/*/ RF LO disabled */\r
+ /*/ RESTORE MAC REG 88C: Enable RF Functions*/\r
+ PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0x0);\r
+ } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {\r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {\r
+ \r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/\r
+ } else {\r
+ /*/ S0/S1 both use PATH A to configure*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/\r
+ }\r
+ } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {\r
+ \r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */\r
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */\r
+ }\r
+ } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); /*Tx mode*/\r
+ PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); /*RF LO disabled*/\r
+ /*Set BB REG 88C: Prevent SingleTone Fail*/\r
+ PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
+ } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+ u1Byte p = ODM_RF_PATH_A;\r
+ \r
+ PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x3); /*/ Disable CCK and OFDM*/\r
+\r
+ if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {\r
+ for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { \r
+ PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);\r
+ PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/\r
+ }\r
+ } else {\r
+ PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);\r
+ PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/\r
+ }\r
+ \r
+ PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0); \r
+ PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1); \r
+ PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord, regBB2);\r
+ PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord, regBB3);\r
+#endif\r
+ }\r
+#ifdef CONFIG_RTL8814A \r
+ else if (IS_HARDWARE_TYPE_8814A(pAdapter))\r
+ mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);\r
+\r
+ else/*/ Turn off all test modes.*/ \r
+ PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF); \r
+#endif\r
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
+\r
+ }\r
+}\r
+\r
+\r
+void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)\r
+{\r
+ u8 Rate;\r
+ pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;\r
+\r
+ Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);\r
+ if (bStart) {/* Start Carrier Suppression.*/\r
+ RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));\r
+ if (Rate <= MPT_RATE_11M) {\r
+ /*/ 1. if CCK block on?*/\r
+ if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/\r
+\r
+ /*/Turn Off All Test Mode*/\r
+ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)\r
+ PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);/* rSingleTone_ContTx_Jaguar*/\r
+ else\r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
+\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/\r
+\r
+ /*/Set CCK Tx Test Rate*/\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/\r
+ }\r
+\r
+ /*Set for dynamic set Power index*/\r
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
+\r
+ } else {/* Stop Carrier Suppression.*/ \r
+ RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));\r
+\r
+ if (Rate <= MPT_RATE_11M) {\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/\r
+\r
+ /*BB Reset*/\r
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
+ }\r
+ /*Stop for dynamic set Power index*/\r
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ }\r
+ DBG_871X("\n MPT_ProSetCarrierSupp() is finished.\n");\r
+}\r
+\r
+void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)\r
+{\r
+ u32 cckrate;\r
+\r
+ if (bStart) {\r
+ RT_TRACE(_module_mp_, _drv_alert_,\r
+ ("SetCCKContinuousTx: test start\n"));\r
+\r
+ /*/ 1. if CCK block on?*/\r
+ if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/\r
+\r
+ /*/Turn Off All Test Mode*/\r
+ if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))\r
+ PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);/*rSingleTone_ContTx_Jaguar*/\r
+ else\r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
+\r
+ /*/Set CCK Tx Test Rate*/\r
+\r
+ cckrate = pAdapter->mppriv.rateidx;\r
+\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/\r
+\r
+ if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {\r
+ PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 11 force cck rxiq = 0*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /*/ 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);\r
+ PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);\r
+ }\r
+\r
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
+\r
+ } else {\r
+ RT_TRACE(_module_mp_, _drv_info_,\r
+ ("SetCCKContinuousTx: test stop\n"));\r
+\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*/normal mode*/\r
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/\r
+\r
+ if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /* && !IS_HARDWARE_TYPE_8822B(pAdapter) */) {\r
+ PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/* rCCK0_RxHP 0xa15[1:0] = 2b00*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /*/ 0xc08[16] = 0*/\r
+ \r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);\r
+ PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);\r
+ }\r
+ \r
+ /*/BB Reset*/\r
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
+\r
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ }\r
+\r
+ pAdapter->mppriv.MptCtx.bCckContTx = bStart;\r
+ pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;\r
+}\r
+\r
+void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+\r
+ if (bStart) {\r
+ RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));/*/ 1. if OFDM block on?*/\r
+ if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
+ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*/set OFDM block on*/\r
+\r
+ /*/ 2. set CCK test mode off, set to CCK normal mode*/\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);\r
+\r
+ /*/ 3. turn on scramble setting*/\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);\r
+\r
+ if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&& !IS_HARDWARE_TYPE_8822B(pAdapter)*/) {\r
+ PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 2b'11*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/\r
+ }\r
+\r
+ /*/ 4. Turn On Continue Tx and turn off the other test modes.*/\r
+ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)\r
+ PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ContinuousTx);/*rSingleTone_ContTx_Jaguar*/\r
+ else\r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ContinuousTx);\r
+\r
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
+\r
+ } else {\r
+ RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));\r
+ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)\r
+ PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
+ else\r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
+ /*/Delay 10 ms*/\r
+ rtw_msleep_os(10);\r
+ \r
+ if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&&! IS_HARDWARE_TYPE_8822B(pAdapter)*/) {\r
+ PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/*/ 0xa15[1:0] = 0*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);/*/ 0xc08[16] = 0*/\r
+ }\r
+ \r
+ /*/BB Reset*/\r
+ PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
+ PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
+\r
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ }\r
+\r
+ pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;\r
+ pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;\r
+}\r
+\r
+void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)\r
+{\r
+ u8 Rate;\r
+ RT_TRACE(_module_mp_, _drv_info_,\r
+ ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));\r
+\r
+ Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);\r
+ pAdapter->mppriv.MptCtx.bStartContTx = bStart;\r
+\r
+ if (Rate <= MPT_RATE_11M)\r
+ hal_mpt_SetCCKContinuousTx(pAdapter, bStart);\r
+ else if (Rate >= MPT_RATE_6M) \r
+ hal_mpt_SetOFDMContinuousTx(pAdapter, bStart);\r
+}\r
+\r
+u32 hal_mpt_query_phytxok(PADAPTER pAdapter)\r
+{\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;\r
+ u16 count = 0;\r
+\r
+ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))\r
+ count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/\r
+ else\r
+ count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/\r
+\r
+ if (count > 50000) {\r
+ rtw_reset_phy_trx_ok_counters(pAdapter);\r
+ pAdapter->mppriv.tx.sended += count;\r
+ count = 0;\r
+ }\r
+\r
+ return pAdapter->mppriv.tx.sended + count;\r
+\r
+}\r
+\r
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B)\r
+/* for HW TX mode */\r
+static VOID mpt_StopCckContTx(\r
+ PADAPTER pAdapter\r
+ )\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ u1Byte u1bReg;\r
+\r
+ pMptCtx->bCckContTx = FALSE;\r
+ pMptCtx->bOfdmContTx = FALSE;\r
+\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/\r
+\r
+ if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {\r
+ PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/\r
+ \r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);\r
+ PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);\r
+ }\r
+\r
+ /*BB Reset*/\r
+ PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
+ PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
+\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
+\r
+} /* mpt_StopCckContTx */\r
+\r
+\r
+static VOID mpt_StopOfdmContTx(\r
+ PADAPTER pAdapter\r
+ )\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ u1Byte u1bReg;\r
+ u4Byte data;\r
+\r
+ pMptCtx->bCckContTx = FALSE;\r
+ pMptCtx->bOfdmContTx = FALSE;\r
+\r
+ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))\r
+ PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
+ else\r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
+\r
+ rtw_mdelay_os(10);\r
+\r
+ if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {\r
+ PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/\r
+ }\r
+\r
+ /*BB Reset*/\r
+ PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
+ PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
+\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
+} /* mpt_StopOfdmContTx */\r
+\r
+\r
+static VOID mpt_StartCckContTx(\r
+ PADAPTER pAdapter\r
+ )\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+ u4Byte cckrate;\r
+\r
+ /* 1. if CCK block on */\r
+ if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
+ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/\r
+\r
+ /*Turn Off All Test Mode*/\r
+ if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))\r
+ PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
+ else\r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
+\r
+ cckrate = pAdapter->mppriv.rateidx;\r
+\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);\r
+\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/\r
+\r
+ if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {\r
+ PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);\r
+ PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);\r
+ }\r
+\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
+\r
+ pMptCtx->bCckContTx = TRUE;\r
+ pMptCtx->bOfdmContTx = FALSE;\r
+ \r
+} /* mpt_StartCckContTx */\r
+\r
+\r
+static VOID mpt_StartOfdmContTx(\r
+ PADAPTER pAdapter\r
+ )\r
+{\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);\r
+\r
+ /* 1. if OFDM block on?*/\r
+ if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
+ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/\r
+\r
+ /* 2. set CCK test mode off, set to CCK normal mode*/\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);\r
+\r
+ /* 3. turn on scramble setting*/\r
+ PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);\r
+\r
+ if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {\r
+ PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/\r
+ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/\r
+ }\r
+\r
+ /* 4. Turn On Continue Tx and turn off the other test modes.*/\r
+ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))\r
+ PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ContinuousTx);\r
+ else\r
+ PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ContinuousTx);\r
+ \r
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
+\r
+ pMptCtx->bCckContTx = FALSE;\r
+ pMptCtx->bOfdmContTx = TRUE;\r
+} /* mpt_StartOfdmContTx */\r
+\r
+\r
+void mpt_ProSetPMacTx(PADAPTER Adapter)\r
+{\r
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);\r
+ RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;\r
+ u32 u4bTmp;\r
+\r
+ DbgPrint("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);\r
+ DbgPrint("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);\r
+#if 0\r
+ PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);\r
+ PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);\r
+ PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);\r
+ PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);\r
+ DbgPrint("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);\r
+ PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);\r
+\r
+ PRINT_DATA("Src Address", Adapter->mac_addr, 6);\r
+ PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6);\r
+#endif\r
+\r
+ if (PMacTxInfo.bEnPMacTx == FALSE) {\r
+ if (PMacTxInfo.Mode == CONTINUOUS_TX) {\r
+ PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/\r
+ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))\r
+ mpt_StopCckContTx(Adapter);\r
+ else\r
+ mpt_StopOfdmContTx(Adapter);\r
+ } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {\r
+ u4bTmp = PHY_QueryBBReg(Adapter, 0xf50, bMaskLWord);\r
+ PHY_SetBBReg(Adapter, 0xb1c, bMaskLWord, u4bTmp+50);\r
+ PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/\r
+ } else\r
+ PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/\r
+\r
+ if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {\r
+ /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/\r
+ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))\r
+ mpt_StopCckContTx(Adapter);\r
+ else\r
+ mpt_StopOfdmContTx(Adapter);\r
+\r
+ mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);\r
+ }\r
+\r
+ return;\r
+ }\r
+\r
+ if (PMacTxInfo.Mode == CONTINUOUS_TX) {\r
+ PMacTxInfo.PacketCount = 1;\r
+\r
+ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))\r
+ mpt_StartCckContTx(Adapter);\r
+ else\r
+ mpt_StartOfdmContTx(Adapter);\r
+ } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {\r
+ /* Continuous TX -> HW TX -> RF Setting */\r
+ PMacTxInfo.PacketCount = 1;\r
+\r
+ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))\r
+ mpt_StartCckContTx(Adapter);\r
+ else\r
+ mpt_StartOfdmContTx(Adapter);\r
+ } else if (PMacTxInfo.Mode == PACKETS_TX) {\r
+ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)\r
+ PMacTxInfo.PacketCount = 0xffff;\r
+ }\r
+\r
+ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {\r
+ /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/\r
+ u4bTmp = PMacTxInfo.PacketCount|(PMacTxInfo.SFD << 16);\r
+ PHY_SetBBReg(Adapter, 0xb1c, bMaskDWord, u4bTmp);\r
+ /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/\r
+ u4bTmp = PMacTxInfo.SignalField|(PMacTxInfo.ServiceField << 8)|(PMacTxInfo.LENGTH << 16);\r
+ PHY_SetBBReg(Adapter, 0xb40, bMaskDWord, u4bTmp);\r
+ u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);\r
+ PHY_SetBBReg(Adapter, 0xb44, bMaskLWord, u4bTmp);\r
+\r
+ if (PMacTxInfo.bSPreamble)\r
+ PHY_SetBBReg(Adapter, 0xb0c, BIT27, 0); \r
+ else\r
+ PHY_SetBBReg(Adapter, 0xb0c, BIT27, 1); \r
+ } else {\r
+ PHY_SetBBReg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);\r
+\r
+ u4bTmp = PMacTxInfo.LSIG[0]|((PMacTxInfo.LSIG[1]) << 8)|((PMacTxInfo.LSIG[2]) << 16)|((PMacTxInfo.PacketPattern) << 24);\r
+ PHY_SetBBReg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/\r
+\r
+ if (PMacTxInfo.PacketPattern == 0x12)\r
+ u4bTmp = 0x3000000;\r
+ else\r
+ u4bTmp = 0;\r
+ }\r
+\r
+ if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {\r
+ u4bTmp |= PMacTxInfo.HT_SIG[0]|((PMacTxInfo.HT_SIG[1]) << 8)|((PMacTxInfo.HT_SIG[2]) << 16);\r
+ PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);\r
+ u4bTmp = PMacTxInfo.HT_SIG[3]|((PMacTxInfo.HT_SIG[4]) << 8)|((PMacTxInfo.HT_SIG[5]) << 16);\r
+ PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);\r
+ } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {\r
+ u4bTmp |= PMacTxInfo.VHT_SIG_A[0]|((PMacTxInfo.VHT_SIG_A[1]) << 8)|((PMacTxInfo.VHT_SIG_A[2]) << 16);\r
+ PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);\r
+ u4bTmp = PMacTxInfo.VHT_SIG_A[3]|((PMacTxInfo.VHT_SIG_A[4]) << 8)|((PMacTxInfo.VHT_SIG_A[5]) << 16);\r
+ PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);\r
+\r
+ _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);\r
+ PHY_SetBBReg(Adapter, 0xb14, bMaskDWord, u4bTmp);\r
+ }\r
+\r
+ if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {\r
+ u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24)|PMacTxInfo.PacketPeriod; /* for TX interval */\r
+ PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, u4bTmp);\r
+\r
+ _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);\r
+ PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, u4bTmp);\r
+\r
+ /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/\r
+ /*& Duration & Frame control*/\r
+ PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, 0x00000040);\r
+\r
+ /* Address1 [0:3]*/\r
+ u4bTmp = PMacTxInfo.MacAddress[0]|(PMacTxInfo.MacAddress[1] << 8)|(PMacTxInfo.MacAddress[2] << 16)|(PMacTxInfo.MacAddress[3] << 24);\r
+ PHY_SetBBReg(Adapter, 0xb2C, bMaskDWord, u4bTmp);\r
+\r
+ /* Address3 [3:0]*/\r
+ PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);\r
+\r
+ /* Address2[0:1] & Address1 [5:4]*/\r
+ u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8)|(Adapter->mac_addr[0] << 16)|(Adapter->mac_addr[1] << 24);\r
+ PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);\r
+\r
+ /* Address2 [5:2]*/\r
+ u4bTmp = Adapter->mac_addr[2]|(Adapter->mac_addr[3] << 8)|(Adapter->mac_addr[4] << 16)|(Adapter->mac_addr[5] << 24);\r
+ PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);\r
+\r
+ /* Sequence Control & Address3 [5:4]*/\r
+ /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/\r
+ /*PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/\r
+ } else {\r
+ PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/\r
+ /* & Duration & Frame control */\r
+ PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, 0x00000040);\r
+\r
+ /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/\r
+ /* Address1 [0:3]*/\r
+ u4bTmp = PMacTxInfo.MacAddress[0]|(PMacTxInfo.MacAddress[1] << 8)|(PMacTxInfo.MacAddress[2] << 16)|(PMacTxInfo.MacAddress[3] << 24);\r
+ PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, u4bTmp);\r
+\r
+ /* Address3 [3:0]*/\r
+ PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);\r
+\r
+ /* Address2[0:1] & Address1 [5:4]*/\r
+ u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8)|(Adapter->mac_addr[0] << 16)|(Adapter->mac_addr[1] << 24);\r
+ PHY_SetBBReg(Adapter, 0xb2c, bMaskDWord, u4bTmp);\r
+\r
+ /* Address2 [5:2] */\r
+ u4bTmp = Adapter->mac_addr[2]|(Adapter->mac_addr[3] << 8)|(Adapter->mac_addr[4] << 16)|(Adapter->mac_addr[5] << 24);\r
+ PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);\r
+\r
+ /* Sequence Control & Address3 [5:4]*/\r
+ u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);\r
+ PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);\r
+ }\r
+\r
+ PHY_SetBBReg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);\r
+\r
+ /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/\r
+ u4bTmp = (PMacTxInfo.TX_SC)|((PMacTxInfo.BandWidth) << 4)|((PMacTxInfo.m_STBC - 1) << 6)|((PMacTxInfo.NDP_sound) << 8);\r
+ PHY_SetBBReg(Adapter, 0xb4c, 0x1ff, u4bTmp);\r
+\r
+ if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) {\r
+ u4Byte offset = 0xb44;\r
+\r
+ if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))\r
+ PHY_SetBBReg(Adapter, offset, 0xc0000000, 0);\r
+ else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))\r
+ PHY_SetBBReg(Adapter, offset, 0xc0000000, 1);\r
+ else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))\r
+ PHY_SetBBReg(Adapter, offset, 0xc0000000, 2);\r
+ }\r
+\r
+ PHY_SetBBReg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/\r
+/* //PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); //TX Stop*/\r
+ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {\r
+ PHY_SetBBReg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/ \r
+ PHY_SetBBReg(Adapter, 0xA84, BIT31, 0);\r
+ } else\r
+ PHY_SetBBReg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */\r
+\r
+ if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)\r
+ mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);\r
+\r
+}\r
+#endif\r
+\r
+#endif /* CONFIG_MP_INCLUDE*/\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff