--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+/*++\r
+Copyright (c) Realtek Semiconductor Corp. All rights reserved.\r
+\r
+Module Name:\r
+ HalPwrSeqCmd.c\r
+\r
+Abstract:\r
+ Implement HW Power sequence configuration CMD handling routine for Realtek devices.\r
+\r
+Major Change History:\r
+ When Who What\r
+ ---------- --------------- -------------------------------\r
+ 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.\r
+ 2011-07-07 Roger Create.\r
+\r
+--*/\r
+#include <HalPwrSeqCmd.h>\r
+\r
+\r
+//\r
+// Description:\r
+// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.\r
+//\r
+// Assumption:\r
+// We should follow specific format which was released from HW SD.\r
+//\r
+// 2011.07.07, added by Roger.\r
+//\r
+u8 HalPwrSeqCmdParsing(\r
+ PADAPTER padapter,\r
+ u8 CutVersion,\r
+ u8 FabVersion,\r
+ u8 InterfaceType,\r
+ WLAN_PWR_CFG PwrSeqCmd[])\r
+{\r
+ WLAN_PWR_CFG PwrCfgCmd = {0};\r
+ u8 bPollingBit = _FALSE;\r
+ u32 AryIdx = 0;\r
+ u8 value = 0;\r
+ u32 offset = 0;\r
+ u32 pollingCount = 0; // polling autoload done.\r
+ u32 maxPollingCnt = 5000;\r
+\r
+ do {\r
+ PwrCfgCmd = PwrSeqCmd[AryIdx];\r
+\r
+ RT_TRACE(_module_hal_init_c_ , _drv_info_,\r
+ ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",\r
+ GET_PWR_CFG_OFFSET(PwrCfgCmd),\r
+ GET_PWR_CFG_CUT_MASK(PwrCfgCmd),\r
+ GET_PWR_CFG_FAB_MASK(PwrCfgCmd),\r
+ GET_PWR_CFG_INTF_MASK(PwrCfgCmd),\r
+ GET_PWR_CFG_BASE(PwrCfgCmd),\r
+ GET_PWR_CFG_CMD(PwrCfgCmd),\r
+ GET_PWR_CFG_MASK(PwrCfgCmd),\r
+ GET_PWR_CFG_VALUE(PwrCfgCmd)));\r
+\r
+ //2 Only Handle the command whose FAB, CUT, and Interface are matched\r
+ if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&\r
+ (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&\r
+ (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))\r
+ {\r
+ switch (GET_PWR_CFG_CMD(PwrCfgCmd))\r
+ {\r
+ case PWR_CMD_READ:\r
+ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));\r
+ break;\r
+\r
+ case PWR_CMD_WRITE:\r
+ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));\r
+ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);\r
+\r
+#ifdef CONFIG_SDIO_HCI\r
+ //\r
+ // <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface\r
+ // 2011.07.07.\r
+ //\r
+ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\r
+ {\r
+ // Read Back SDIO Local value\r
+ value = SdioLocalCmd52Read1Byte(padapter, offset);\r
+\r
+ value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));\r
+ value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));\r
+\r
+ // Write Back SDIO Local value\r
+ SdioLocalCmd52Write1Byte(padapter, offset, value);\r
+ }\r
+ else\r
+#endif\r
+ {\r
+#ifdef CONFIG_GSPI_HCI\r
+ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\r
+ offset = SPI_LOCAL_OFFSET | offset;\r
+#endif\r
+ // Read the value from system register\r
+ value = rtw_read8(padapter, offset);\r
+\r
+ value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));\r
+ value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));\r
+\r
+ // Write the value back to sytem register\r
+ rtw_write8(padapter, offset, value);\r
+ }\r
+ break;\r
+\r
+ case PWR_CMD_POLLING:\r
+ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));\r
+\r
+ bPollingBit = _FALSE;\r
+ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);\r
+#ifdef CONFIG_GSPI_HCI\r
+ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\r
+ offset = SPI_LOCAL_OFFSET | offset;\r
+#endif\r
+ do {\r
+#ifdef CONFIG_SDIO_HCI\r
+ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\r
+ value = SdioLocalCmd52Read1Byte(padapter, offset);\r
+ else\r
+#endif\r
+ value = rtw_read8(padapter, offset);\r
+\r
+ value=value&GET_PWR_CFG_MASK(PwrCfgCmd);\r
+ if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))\r
+ bPollingBit = _TRUE;\r
+ else\r
+ rtw_udelay_os(10);\r
+\r
+ if (pollingCount++ > maxPollingCnt) {\r
+ DBG_871X_LEVEL(_drv_err_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);\r
+ return _FALSE;\r
+ }\r
+ } while (!bPollingBit);\r
+\r
+ break;\r
+\r
+ case PWR_CMD_DELAY:\r
+ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));\r
+ if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)\r
+ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));\r
+ else\r
+ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);\r
+ break;\r
+\r
+ case PWR_CMD_END:\r
+ // When this command is parsed, end the process\r
+ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));\r
+ return _TRUE;\r
+ break;\r
+\r
+ default:\r
+ RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));\r
+ break;\r
+ }\r
+ }\r
+\r
+ AryIdx++;//Add Array Index\r
+ }while(1);\r
+\r
+ return _TRUE;\r
+}\r
+\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff