// 0x0000h ~ 0x00FFh System Configuration\r
//\r
//-----------------------------------------------------\r
+#define REG_SYS_SWR_CTRL1_8192E 0x0010 // 1 Byte \r
+#define REG_SYS_SWR_CTRL2_8192E 0x0014 // 1 Byte \r
#define REG_AFE_CTRL1_8192E 0x0024\r
#define REG_AFE_CTRL2_8192E 0x0028\r
#define REG_AFE_CTRL3_8192E 0x002c\r
\r
-\r
+#define REG_PAD_CTRL1_8192E 0x0064 \r
#define REG_SDIO_CTRL_8192E 0x0070\r
#define REG_OPT_CTRL_8192E 0x0074\r
#define REG_RF_B_CTRL_8192E 0x0076\r
// 0x0200h ~ 0x027Fh TXDMA Configuration\r
//\r
//-----------------------------------------------------\r
+#define REG_DWBCN0_CTRL 0x0208\r
+#define REG_DWBCN1_CTRL 0x0228\r
\r
//-----------------------------------------------------\r
//\r
// 0x0300h ~ 0x03FFh PCIe\r
//\r
//-----------------------------------------------------\r
-#define REG_PCIE_MULTIFET_CTRL_8192E 0x036A //PCIE Multi-Fethc Control\r
+#define REG_PCIE_CTRL_REG_8192E 0x0300\r
+#define REG_INT_MIG_8192E 0x0304 // Interrupt Migration \r
+#define REG_BCNQ_TXBD_DESA_8192E 0x0308 // TX Beacon Descriptor Address\r
+#define REG_MGQ_TXBD_DESA_8192E 0x0310 // TX Manage Queue Descriptor Address\r
+#define REG_VOQ_TXBD_DESA_8192E 0x0318 // TX VO Queue Descriptor Address\r
+#define REG_VIQ_TXBD_DESA_8192E 0x0320 // TX VI Queue Descriptor Address\r
+#define REG_BEQ_TXBD_DESA_8192E 0x0328 // TX BE Queue Descriptor Address\r
+#define REG_BKQ_TXBD_DESA_8192E 0x0330 // TX BK Queue Descriptor Address\r
+#define REG_RXQ_RXBD_DESA_8192E 0x0338 // RX Queue Descriptor Address\r
+#define REG_HI0Q_TXBD_DESA_8192E 0x0340\r
+#define REG_HI1Q_TXBD_DESA_8192E 0x0348\r
+#define REG_HI2Q_TXBD_DESA_8192E 0x0350\r
+#define REG_HI3Q_TXBD_DESA_8192E 0x0358\r
+#define REG_HI4Q_TXBD_DESA_8192E 0x0360\r
+#define REG_HI5Q_TXBD_DESA_8192E 0x0368\r
+#define REG_HI6Q_TXBD_DESA_8192E 0x0370\r
+#define REG_HI7Q_TXBD_DESA_8192E 0x0378\r
+#define REG_MGQ_TXBD_NUM_8192E 0x0380\r
+#define REG_RX_RXBD_NUM_8192E 0x0382\r
+#define REG_VOQ_TXBD_NUM_8192E 0x0384\r
+#define REG_VIQ_TXBD_NUM_8192E 0x0386\r
+#define REG_BEQ_TXBD_NUM_8192E 0x0388\r
+#define REG_BKQ_TXBD_NUM_8192E 0x038A\r
+#define REG_HI0Q_TXBD_NUM_8192E 0x038C\r
+#define REG_HI1Q_TXBD_NUM_8192E 0x038E\r
+#define REG_HI2Q_TXBD_NUM_8192E 0x0390\r
+#define REG_HI3Q_TXBD_NUM_8192E 0x0392\r
+#define REG_HI4Q_TXBD_NUM_8192E 0x0394\r
+#define REG_HI5Q_TXBD_NUM_8192E 0x0396\r
+#define REG_HI6Q_TXBD_NUM_8192E 0x0398\r
+#define REG_HI7Q_TXBD_NUM_8192E 0x039A\r
+#define REG_TSFTIMER_HCI_8192E 0x039C\r
+\r
+//Read Write Point\r
+#define REG_VOQ_TXBD_IDX_8192E 0x03A0\r
+#define REG_VIQ_TXBD_IDX_8192E 0x03A4\r
+#define REG_BEQ_TXBD_IDX_8192E 0x03A8\r
+#define REG_BKQ_TXBD_IDX_8192E 0x03AC\r
+#define REG_MGQ_TXBD_IDX_8192E 0x03B0\r
+#define REG_RXQ_TXBD_IDX_8192E 0x03B4\r
+#define REG_HI0Q_TXBD_IDX_8192E 0x03B8\r
+#define REG_HI1Q_TXBD_IDX_8192E 0x03BC\r
+#define REG_HI2Q_TXBD_IDX_8192E 0x03C0\r
+#define REG_HI3Q_TXBD_IDX_8192E 0x03C4\r
+#define REG_HI4Q_TXBD_IDX_8192E 0x03C8\r
+#define REG_HI5Q_TXBD_IDX_8192E 0x03CC\r
+#define REG_HI6Q_TXBD_IDX_8192E 0x03D0\r
+#define REG_HI7Q_TXBD_IDX_8192E 0x03D4\r
+\r
+#define REG_PCIE_HCPWM_8192EE 0x03D8 // ??????\r
+#define REG_PCIE_HRPWM_8192EE 0x03DC //PCIe RPWM // ??????\r
+#define REG_DBI_WDATA_V1_8192E 0x03E8\r
+#define REG_DBI_RDATA_V1_8192E 0x03EC\r
+#define REG_DBI_FLAG_V1_8192E 0x03F0\r
+#define REG_MDIO_V1_8192E 0x3F4\r
+#define REG_PCIE_MIX_CFG_8192E 0x3F8\r
\r
//-----------------------------------------------------\r
//\r
//\r
//-----------------------------------------------------\r
#define REG_TXBF_CTRL_8192E 0x042C\r
+#define REG_ARFR0_8192E 0x0444\r
#define REG_ARFR1_8192E 0x044C\r
#define REG_CCK_CHECK_8192E 0x0454\r
#define REG_AMPDU_MAX_TIME_8192E 0x0456\r
#define REG_BCNQ1_BDNY_8192E 0x0457\r
\r
#define REG_AMPDU_MAX_LENGTH_8192E 0x0458\r
+#define REG_WMAC_LBK_BUF_HD_8192E 0x045D\r
#define REG_NDPA_OPT_CTRL_8192E 0x045F\r
#define REG_DATA_SC_8192E 0x0483\r
+#ifdef CONFIG_WOWLAN\r
+#define REG_TXPKTBUF_IV_LOW 0x0484\r
+#define REG_TXPKTBUF_IV_HIGH 0x0488\r
+#endif\r
+#define REG_ARFR2_8192E 0x048C\r
+#define REG_ARFR3_8192E 0x0494\r
#define REG_TXRPT_START_OFFSET 0x04AC\r
#define REG_AMPDU_BURST_MODE_8192E 0x04BC\r
#define REG_HT_SINGLE_AMPDU_8192E 0x04C7\r
#define AcmHw_ViqStatus_8192E BIT(6)\r
#define AcmHw_BeqStatus_8192E BIT(7)\r
\r
+//========================================================\r
+// General definitions\r
+//========================================================\r
\r
-\r
+#define MACID_NUM_8192E 128\r
+#define SEC_CAM_ENT_NUM_8192E 64\r
+#define NSS_NUM_8192E 2\r
+#define BAND_CAP_8192E (BAND_CAP_2G)\r
+#define BW_CAP_8192E (BW_CAP_20M | BW_CAP_40M)\r
+#define PROTO_CAP_8192E (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N)\r
\r
#endif //__RTL8192E_SPEC_H__\r
\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff