#if 1//def CONFIG_SINGLE_IMG
-#include "../hal/OUTSRC/odm_precomp.h"
+#include "../hal/phydm/phydm_precomp.h"
#ifdef CONFIG_BT_COEXIST
#include <hal_btcoex.h>
#endif
#ifdef CONFIG_SDIO_HCI
#include <hal_sdio.h>
#endif
-
+#ifdef CONFIG_GSPI_HCI
+#include <hal_gspi.h>
+#endif
//
// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
//
RT_AMPDU_BRUST_8723B = 7,
}RT_AMPDU_BRUST,*PRT_AMPDU_BRUST_MODE;
+/*
#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number
-#define CHANNEL_MAX_NUMBER_2G 14
-#define CHANNEL_MAX_NUMBER_5G 54 // Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A"
-#define CHANNEL_MAX_NUMBER_5G_80M 7
-#define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups
-#define MAX_PG_GROUP 13
+*/
+#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14 total three groups */
+#define MAX_PG_GROUP 13
// Tx Power Limit Table Size
#define MAX_REGULATION_NUM 4
#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4
-#define MAX_2_4G_BANDWITH_NUM 2
+#define MAX_2_4G_BANDWIDTH_NUM 2
#define MAX_RATE_SECTION_NUM 10
-#define MAX_5G_BANDWITH_NUM 4
+#define MAX_5G_BANDWIDTH_NUM 4
#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1,OFDM:1, HT:4, VHT:4
#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4
//#define HP_THERMAL_NUM 8
//###### duplicate code,will move to ODM #########
-#if defined(CONFIG_RTL8192D) || defined(CONFIG_BT_COEXIST)
-typedef enum _MACPHY_MODE_8192D{
- SINGLEMAC_SINGLEPHY, //SMSP
- DUALMAC_DUALPHY, //DMDP
- DUALMAC_SINGLEPHY, //DMSP
-}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
-#endif
-
#ifdef CONFIG_USB_RX_AGGREGATION
typedef enum _USB_RX_AGG_MODE{
USB_RX_AGG_DISABLE,
#endif
+/* For store initial value of BB register */
+typedef struct _BB_INIT_REGISTER {
+ u16 offset;
+ u32 value;
+
+} BB_INIT_REGISTER, *PBB_INIT_REGISTER;
+
#define PAGE_SIZE_128 128
#define PAGE_SIZE_256 256
#define PAGE_SIZE_512 512
-struct dm_priv
-{
- u8 DM_Type;
+#define HCI_SUS_ENTER 0
+#define HCI_SUS_LEAVING 1
+#define HCI_SUS_LEAVE 2
+#define HCI_SUS_ENTERING 3
+#define HCI_SUS_ERR 4
+
+#ifdef CONFIG_AUTO_CHNL_SEL_NHM
+typedef enum _ACS_OP {
+ ACS_INIT, /*ACS - Variable init*/
+ ACS_RESET, /*ACS - NHM Counter reset*/
+ ACS_SELECT, /*ACS - NHM Counter Statistics */
+} ACS_OP;
+
+typedef enum _ACS_STATE {
+ ACS_DISABLE,
+ ACS_ENABLE,
+} ACS_STATE;
+
+struct auto_chan_sel {
+ ATOMIC_T state;
+ u8 ch; /* previous channel*/
+};
+#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
-#define DYNAMIC_FUNC_BT BIT0
+#define EFUSE_FILE_UNUSED 0
+#define EFUSE_FILE_FAILED 1
+#define EFUSE_FILE_LOADED 2
- u8 DMFlag;
- u8 InitDMFlag;
- //u8 RSVD_1;
-
- u32 InitODMFlag;
- //* Upper and Lower Signal threshold for Rate Adaptive*/
- int UndecoratedSmoothedPWDB;
- int UndecoratedSmoothedCCK;
- int EntryMinUndecoratedSmoothedPWDB;
- int EntryMaxUndecoratedSmoothedPWDB;
- int MinUndecoratedPWDBForDM;
- int LastMinUndecoratedPWDBForDM;
+#define MACADDR_FILE_UNUSED 0
+#define MACADDR_FILE_FAILED 1
+#define MACADDR_FILE_LOADED 2
- s32 UndecoratedSmoothedBeacon;
+#define KFREE_FLAG_ON BIT0
+#define KFREE_FLAG_THERMAL_K_ON BIT1
-//###### duplicate code,will move to ODM #########
- //for High Power
- u8 bDynamicTxPowerEnable;
- u8 LastDTPLvl;
- u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
-
- //for tx power tracking
- u8 bTXPowerTracking;
- u8 TXPowercount;
- u8 bTXPowerTrackingInit;
- u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
- u8 TM_Trigger;
-
- u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
- u8 ThermalValue;
- u8 ThermalValue_LCK;
- u8 ThermalValue_IQK;
- u8 ThermalValue_DPK;
- u8 bRfPiEnable;
- //u8 RSVD_2;
-
- //for APK
- u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
- u8 bAPKdone;
- u8 bAPKThermalMeterIgnore;
- u8 bDPdone;
- u8 bDPPathAOK;
- u8 bDPPathBOK;
- //u8 RSVD_3;
- //u8 RSVD_4;
- //u8 RSVD_5;
-
- //for IQK
- u32 ADDA_backup[IQK_ADDA_REG_NUM];
- u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
- u32 IQK_BB_backup_recover[9];
- u32 IQK_BB_backup[IQK_BB_REG_NUM];
-
- u8 PowerIndex_backup[6];
- u8 OFDM_index[2];
-
- u8 bCCKinCH14;
- u8 CCK_index;
- u8 bDoneTxpower;
- u8 CCK_index_HP;
-
- u8 OFDM_index_HP[2];
- u8 ThermalValue_HP[HP_THERMAL_NUM];
- u8 ThermalValue_HP_index;
- //u8 RSVD_6;
-
- //for TxPwrTracking2
- s32 RegE94;
- s32 RegE9C;
- s32 RegEB4;
- s32 RegEBC;
-
- u32 TXPowerTrackingCallbackCnt; //cosa add for debug
-
- u32 prv_traffic_idx; // edca turbo
-#ifdef CONFIG_RTL8192D
- u8 ThermalValue_AVG[AVG_THERMAL_NUM];
- u8 ThermalValue_AVG_index;
- u8 ThermalValue_RxGain;
- u8 ThermalValue_Crystal;
- u8 bReloadtxpowerindex;
-
- u32 RegD04_MP;
-
- u8 RegC04_MP;
- u8 Delta_IQK;
- u8 Delta_LCK;
- //u8 RSVD_7;
-
- BOOLEAN bDPKdone[2];
- //u16 RSVD_8;
-
- u32 RegA24;
- u32 RegRF3C[2]; //pathA / pathB
+#define MAX_IQK_INFO_BACKUP_CHNL_NUM 5
+#define MAX_IQK_INFO_BACKUP_REG_NUM 10
+
+struct kfree_data_t {
+ u8 flag;
+ s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ s8 pa_bias_5g[RF_PATH_MAX];
+ s8 pad_bias_5g[RF_PATH_MAX];
#endif
-//###### duplicate code,will move to ODM #########
+ s8 thermal;
+};
+
+bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
+
+struct hal_spec_t {
+ u8 macid_num;
- // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
- u8 INIDATA_RATE[32];
+ u8 sec_cam_ent_num;
+ u8 sec_cap;
+
+ u8 nss_num;
+ u8 band_cap; /* value of BAND_CAP_XXX */
+ u8 bw_cap; /* value of BW_CAP_XXX */
+ u8 proto_cap; /* value of PROTO_CAP_XXX */
+
+ u8 wl_func; /* value of WL_FUNC_XXX */
};
+struct hal_iqk_reg_backup {
+ u8 central_chnl;
+ u8 bw_mode;
+ u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];
+};
typedef struct hal_com_data
{
RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
-
+ u8 hw_init_completed;
+ /****** FW related ******/
u16 FirmwareVersion;
u16 FirmwareVersionRev;
u16 FirmwareSubVersion;
u16 FirmwareSignature;
+ u8 RegFWOffload;
+ u8 fw_ractrl;
+ u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/
+ u8 LastHMEBoxNum; /* H2C - for host message to fw */
- //current WIFI_PHY values
- WIRELESS_MODE CurrentWirelessMode;
+ /****** current WIFI_PHY values ******/
+ WIRELESS_MODE CurrentWirelessMode;
CHANNEL_WIDTH CurrentChannelBW;
- BAND_TYPE CurrentBandType; //0:2.4G, 1:5G
- BAND_TYPE BandSet;
- u8 CurrentChannel;
- u8 CurrentCenterFrequencyIndex1;
- u8 nCur40MhzPrimeSC;// Control channel sub-carrier
- u8 nCur80MhzPrimeSC; //used for primary 40MHz of 80MHz mode
-
- u16 CustomerID;
- u16 BasicRateSet;
- u16 ForcedDataRate;// Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M.
- u32 ReceiveConfig;
-
- //rf_ctrl
+ BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */
+ BAND_TYPE BandSet;
+ u8 CurrentChannel;
+ u8 CurrentCenterFrequencyIndex1;
+ u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */
+ u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */
+ BOOLEAN bSwChnlAndSetBWInProgress;
+ u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */
+ u16 BasicRateSet;
+ u32 ReceiveConfig;
+ BOOLEAN bSwChnl;
+ BOOLEAN bSetChnlBW;
+ BOOLEAN bChnlBWInitialized;
+#ifdef CONFIG_AUTO_CHNL_SEL_NHM
+ struct auto_chan_sel acs;
+#endif
+ /****** rf_ctrl *****/
u8 rf_chip;
u8 rf_type;
u8 PackageType;
u8 NumTotalRFPath;
- u8 InterfaceSel;
- u8 framesync;
- u32 framesyncC34;
- u8 framesyncMonitor;
- u8 DefaultInitialGain[4];
- //
- // EEPROM setting.
- //
+ /****** Debug ******/
+ u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
+ u8 u1ForcedIgiLb; /* forced IGI lower bound */
+ u8 bDumpRxPkt;
+ u8 bDumpTxPkt;
+ u8 bDisableTXPowerTraining;
+
+
+ /****** EEPROM setting.******/
+ u8 bautoload_fail_flag;
+ u8 efuse_file_status;
+ u8 macaddr_file_status;
+ u8 EepromOrEfuse;
+ u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
+ u8 InterfaceSel; /* board type kept in eFuse */
+ u16 CustomerID;
+
u16 EEPROMVID;
u16 EEPROMSVID;
#ifdef CONFIG_USB_HCI
u8 EEPROMBluetoothAntIsolation;
u8 EEPROMBluetoothRadioShared;
u8 bTXPowerDataReadFromEEPORM;
- u8 bAPKThermalMeterIgnore;
- u8 bDisableSWChannelPlan; // flag of disable software change channel plan
-
- BOOLEAN EepromOrEfuse;
- u8 EfuseUsedPercentage;
- u16 EfuseUsedBytes;
- //u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];
- EFUSE_HAL EfuseHal;
+ u8 EEPROMMACAddr[ETH_ALEN];
+
+#ifdef CONFIG_RF_POWER_TRIM
+ u8 EEPROMRFGainOffset;
+ u8 EEPROMRFGainVal;
+ struct kfree_data_t kfree_data;
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B)
+ u8 adjuseVoltageVal;
+#endif
+ u8 EfuseUsedPercentage;
+ u16 EfuseUsedBytes;
+ /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
+ EFUSE_HAL EfuseHal;
- //---------------------------------------------------------------------------------//
+ /*---------------------------------------------------------------------------------*/
//3 [2.4G]
- u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
- u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
+ u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
+ u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
//If only one tx, only BW20 and OFDM are used.
s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
//3 [5G]
- u8 Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
- u8 Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
+ u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
+ u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 TxPwrInPercentage;
- u8 TxPwrCalibrateRate;
- //
- // TX power by rate table at most 4RF path.
- // The register is
- //
- // VHT TX power by rate off setArray =
- // Band:-2G&5G = 0 / 1
- // RF: at most 4*4 = ABCD=0/1/2/3
- // CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
- //
+ /********************************
+ * TX power by rate table at most 4RF path.
+ * The register is
+ *
+ * VHT TX power by rate off setArray =
+ * Band:-2G&5G = 0 / 1
+ * RF: at most 4*4 = ABCD=0/1/2/3
+ * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
+ **********************************/
u8 TxPwrByRateTable;
u8 TxPwrByRateBand;
s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
[TX_PWR_BY_RATE_NUM_RATE];
//---------------------------------------------------------------------------------//
+ /*
//2 Power Limit Table
u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
- u8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
+ s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
+ */
+
+ u8 tx_pwr_lmt_5g_20_40_ref;
// Power Limit Table for 2.4G
- u8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
- [MAX_2_4G_BANDWITH_NUM]
- [MAX_RATE_SECTION_NUM]
- [CHANNEL_MAX_NUMBER_2G]
- [MAX_RF_PATH_NUM];
+ s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
+ [MAX_2_4G_BANDWIDTH_NUM]
+ [MAX_RATE_SECTION_NUM]
+ [CENTER_CH_2G_NUM]
+ [MAX_RF_PATH];
// Power Limit Table for 5G
- u8 TxPwrLimit_5G[MAX_REGULATION_NUM]
- [MAX_5G_BANDWITH_NUM]
+ s8 TxPwrLimit_5G[MAX_REGULATION_NUM]
+ [MAX_5G_BANDWIDTH_NUM]
[MAX_RATE_SECTION_NUM]
- [CHANNEL_MAX_NUMBER_5G]
- [MAX_RF_PATH_NUM];
+ [CENTER_CH_5G_ALL_NUM]
+ [MAX_RF_PATH];
// Store the original power by rate value of the base of each rate section of rf path A & B
[TX_PWR_BY_RATE_NUM_RF]
[MAX_BASE_NUM_IN_PHY_REG_PG_5G];
+ u8 txpwr_by_rate_loaded:1;
+ u8 txpwr_by_rate_from_file:1;
+ u8 txpwr_limit_loaded:1;
+ u8 txpwr_limit_from_file:1;
+
// For power group
+ /*
u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
-
-
-
-
+ */
u8 PGMaxGroup;
- u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
+
// The current Tx Power Level
u8 CurrentCckTxPwrIdx;
u8 CurrentOfdm24GTxPwrIdx;
u32 CCKTxPowerLevelOriginalOffset;
u8 CrystalCap;
- u32 AntennaTxPath; // Antenna path Tx
- u32 AntennaRxPath; // Antenna path Rx
-
+
u8 PAType_2G;
u8 PAType_5G;
u8 LNAType_2G;
u8 ExternalLNA_2G;
u8 ExternalPA_5G;
u8 ExternalLNA_5G;
- u8 TypeGLNA;
- u8 TypeGPA;
- u8 TypeALNA;
- u8 TypeAPA;
- u8 RFEType;
- u8 BoardType;
- u8 ExternalPA;
- u8 bIQKInitialized;
- BOOLEAN bLCKInProgress;
+ u16 TypeGLNA;
+ u16 TypeGPA;
+ u16 TypeALNA;
+ u16 TypeAPA;
+ u16 RFEType;
- BOOLEAN bSwChnl;
- BOOLEAN bSetChnlBW;
- BOOLEAN bChnlBWInitialized;
- BOOLEAN bNeedIQK;
+ u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
+ u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
- u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
- u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
- u8 b1x1RecvCombine; // for 1T1R receive combining
+ BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; //Radio A/B/C/D
- u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
-
- BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
-
- u32 RfRegChnlVal[2];
+ u32 RfRegChnlVal[MAX_RF_PATH];
//RDG enable
BOOLEAN bRDGEnable;
- //for host message to fw
- u8 LastHMEBoxNum;
-
- u8 fw_ractrl;
u8 RegTxPause;
// Beacon function related global variable.
u8 RegBcnCtrlVal;
u8 RegReg542;
u8 RegCR_1;
u8 Reg837;
- u8 RegRFPathS1;
u16 RegRRSR;
-
- u8 CurAntenna;
+
+ /****** antenna diversity ******/
u8 AntDivCfg;
u8 AntDetection;
u8 TRxAntDivType;
+ u8 ant_path; //for 8723B s0/s1 selection
+ u32 AntennaTxPath; /* Antenna path Tx */
+ u32 AntennaRxPath; /* Antenna path Rx */
+ u8 sw_antdiv_bl_state;
+
+ /******** PHY DM & DM Section **********/
+ u8 DM_Type;
+ _lock IQKSpinLock;
+ u8 INIDATA_RATE[MACID_NUM_SW_LIMIT];
+ /* Upper and Lower Signal threshold for Rate Adaptive*/
+ int EntryMinUndecoratedSmoothedPWDB;
+ int EntryMaxUndecoratedSmoothedPWDB;
+ int MinUndecoratedPWDBForDM;
+ DM_ODM_T odmpriv;
+ u8 bIQKInitialized;
+ u8 bNeedIQK;
+ /******** PHY DM & DM Section **********/
- u8 u1ForcedIgiLb; // forced IGI lower bound
- u8 bDumpRxPkt;//for debug
- u8 bDumpTxPkt;//for debug
- u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
// 2010/08/09 MH Add CU power down mode.
BOOLEAN pwrdown;
// Add for dual MAC 0--Mac0 1--Mac1
u32 interfaceIndex;
- u8 OutEpQueueSel;
- u8 OutEpNumber;
-
- // 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
- BOOLEAN UsbRxHighSpeedMode;
-
- // 2010/11/22 MH Add for slim combo debug mode selective.
- // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
- BOOLEAN SlimComboDbg;
-
#ifdef CONFIG_P2P
u8 p2p_ps_offload;
#endif
-
- u8 AMPDUDensity;
-
- // Auto FSM to Turn On, include clock, isolation, power control for MAC only
+ /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
u8 bMacPwrCtrlOn;
-
+ u8 hci_sus_state;
+
u8 RegIQKFWOffload;
struct submit_ctx iqk_sctx;
RT_AMPDU_BRUST AMPDUBurstMode; //92C maybe not use, but for compile successfully
-#ifdef CONFIG_SDIO_HCI
+ u8 OutEpQueueSel;
+ u8 OutEpNumber;
+
+#if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
//
// For SDIO Interface HAL related
//
_lock SdioTxFIFOFreePageLock;
u8 SdioTxOQTMaxFreeSpace;
u8 SdioTxOQTFreeSpace;
-
//
// SDIO Rx FIFO related.
#endif //CONFIG_SDIO_HCI
#ifdef CONFIG_USB_HCI
- u32 UsbBulkOutSize;
+
+ // 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
+ BOOLEAN UsbRxHighSpeedMode;
+ BOOLEAN UsbTxVeryHighSpeedMode;
+ u32 UsbBulkOutSize;
BOOLEAN bSupportUSB3;
// Interrupt relatd register information.
- u32 IntArray[3];//HISR0,HISR1,HSISR
- u32 IntrMask[3];
- u8 C2hArray[16];
+ u32 IntArray[3];//HISR0,HISR1,HSISR
+ u32 IntrMask[3];
+ u8 C2hArray[16];
#ifdef CONFIG_USB_TX_AGGREGATION
- u8 UsbTxAggMode;
- u8 UsbTxAggDescNum;
+ u8 UsbTxAggMode;
+ u8 UsbTxAggDescNum;
#endif // CONFIG_USB_TX_AGGREGATION
#ifdef CONFIG_USB_RX_AGGREGATION
- u16 HwRxPageSize; // Hardware setting
- u32 MaxUsbRxAggBlock;
+ u16 HwRxPageSize; // Hardware setting
+ u32 MaxUsbRxAggBlock;
USB_RX_AGG_MODE UsbRxAggMode;
- u8 UsbRxAggBlockCount; //FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
- u8 UsbRxAggBlockTimeout;
- u8 UsbRxAggPageCount; //FOR DMA Mode, 8192C DMA page count
- u8 UsbRxAggPageTimeout;
+ u8 UsbRxAggBlockCount; /* FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed */
+ u8 UsbRxAggBlockTimeout;
+ u8 UsbRxAggPageCount; /* FOR DMA Mode, 8192C DMA page count*/
+ u8 UsbRxAggPageTimeout;
- u8 RegAcUsbDmaSize;
- u8 RegAcUsbDmaTime;
+ u8 RegAcUsbDmaSize;
+ u8 RegAcUsbDmaTime;
#endif//CONFIG_USB_RX_AGGREGATION
#endif //CONFIG_USB_HCI
//
// EEPROM setting.
//
- u16 EEPROMChannelPlan;
-
- u8 EEPROMTSSI[2];
- u8 EEPROMBoardType;
- u32 TransmitConfig;
-
- u32 IntrMaskToSet[2];
- u32 IntArray[2];
- u32 IntrMask[2];
- u32 SysIntArray[1];
- u32 SysIntrMask[1];
- u32 IntrMaskReg[2];
- u32 IntrMaskDefault[2];
-
- BOOLEAN bL1OffSupport;
- BOOLEAN bSupportBackDoor;
-
- u8 bDefaultAntenna;
- //u8 bIQKInitialized;
+ u32 TransmitConfig;
+ u32 IntrMaskToSet[2];
+ u32 IntArray[2];
+ u32 IntrMask[2];
+ u32 SysIntArray[1];
+ u32 SysIntrMask[1];
+ u32 IntrMaskReg[2];
+ u32 IntrMaskDefault[2];
+
+ BOOLEAN bL1OffSupport;
+ BOOLEAN bSupportBackDoor;
+
+ u8 bDefaultAntenna;
- u8 bInterruptMigration;
- u8 bDisableTxInt;
+ u8 bInterruptMigration;
+ u8 bDisableTxInt;
+
+ u16 RxTag;
#endif //CONFIG_PCI_HCI
+
- struct dm_priv dmpriv;
- DM_ODM_T odmpriv;
#ifdef DBG_CONFIG_ERROR_DETECT
struct sreset_priv srestpriv;
#endif //#ifdef DBG_CONFIG_ERROR_DETECT
#ifdef CONFIG_BT_COEXIST
// For bluetooth co-existance
BT_COEXIST bt_coexist;
-#ifdef CONFIG_RTL8723A
- u8 bAntennaDetected;
-#endif // CONFIG_RTL8723A
#endif // CONFIG_BT_COEXIST
-#if defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B)
+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8188F)
#ifndef CONFIG_PCI_HCI // mutual exclusive with PCI -- so they're SDIO and GSPI
// Interrupt relatd register information.
u32 SysIntrStatus;
u32 SysIntrMask;
#endif
-#endif //endif CONFIG_RTL8723A
-
-
-#if defined(CONFIG_RTL8192C) ||defined(CONFIG_RTL8192D)
-
- u8 BluetoothCoexist;
-
- u8 EEPROMChnlAreaTxPwrCCK[2][3];
- u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
- u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
- u8 EEPROMPwrLimitHT20[3];
- u8 EEPROMPwrLimitHT40[3];
- #ifdef CONFIG_RTL8192D
- MACPHY_MODE_8192D MacPhyMode92D;
- BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
- BAND_TYPE BandSet92D;
- BOOLEAN bMasterOfDMSP;
- BOOLEAN bSlaveOfDMSP;
-
- IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM_92D];
- #ifdef CONFIG_DUALMAC_CONCURRENT
- BOOLEAN bInModeSwitchProcess;
- #endif
- u8 AutoLoadStatusFor8192D;
- u8 EEPROMC9;
- u8 EEPROMCC;
- u8 PAMode;
- u8 InternalPA5G[2]; //pathA / pathB
- BOOLEAN bPhyValueInitReady;
- BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress
- BOOLEAN bNOPG;
- BOOLEAN bIsVS;
- //Query RF by FW
- BOOLEAN bReadRFbyFW;
- BOOLEAN bEarlyModeEnable;
- BOOLEAN bSupportRemoteWakeUp;
- BOOLEAN bInSetPower;
- u8 RTSInitRate; // 2010.11.24.by tynli.
- #endif //CONFIG_RTL8192D
-
-#endif //defined(CONFIG_RTL8192C) ||defined(CONFIG_RTL8192D)
+#endif /*endif CONFIG_RTL8723B */
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
char para_file_buf[MAX_PARA_FILE_BUF_LEN];
char *rf_tx_pwr_lmt;
u32 rf_tx_pwr_lmt_len;
#endif
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+ s16 noise[ODM_MAX_CHANNEL_NUM];
+#endif
+
+ struct hal_spec_t hal_spec;
+
+ u8 RfKFreeEnable;
+ u8 RfKFree_ch_group;
+ BOOLEAN bCCKinCH14;
+ BB_INIT_REGISTER RegForRecover[5];
+
+#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
+ BOOLEAN bCorrectBCN;
+#endif
+
+ struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
} HAL_DATA_COMMON, *PHAL_DATA_COMMON;
+
typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
-#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
-#define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath )
-#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
-#define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type)
+#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
+#define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec))
+
+#define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath )
+#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
+#define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type)
+#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
+
+#define SUPPORT_HW_RADIO_DETECT(Adapter) ( RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD ||\
+ RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo ||\
+ RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
+
+#define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr)
+#define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse)
+#define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed)
+#define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
#endif
+#ifdef CONFIG_AUTO_CHNL_SEL_NHM
+#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
+#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
+#define rtw_get_acs_channel(padapter) (GET_HAL_DATA(padapter)->acs.ch)
+#define rtw_set_acs_channel(padapter, survey_ch) (GET_HAL_DATA(padapter)->acs.ch = survey_ch)
+#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
#endif //__HAL_DATA_H__
projects / firefly-linux-kernel-4.4.55.git / blobdiff