return NULL;
}
-static void ath9k_hw_set_defaults(struct ath_hw *ah)
+static void ath9k_hw_init_config(struct ath_hw *ah)
{
int i;
ah->config.cck_trig_high = 200;
ah->config.cck_trig_low = 100;
ah->config.enable_ani = 1;
- ah->config.diversity_control = 0;
+ ah->config.diversity_control = ATH9K_ANT_VARIABLE;
ah->config.antenna_switch_swap = 0;
for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
ah->config.serialize_regmode = SER_REG_MODE_AUTO;
}
-static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
- int *status)
+static void ath9k_hw_init_defaults(struct ath_hw *ah)
{
- struct ath_hw *ah;
+ struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
- ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
- if (ah == NULL) {
- DPRINTF(sc, ATH_DBG_FATAL,
- "Cannot allocate memory for state block\n");
- *status = -ENOMEM;
- return NULL;
- }
+ regulatory->country_code = CTRY_DEFAULT;
+ regulatory->power_limit = MAX_RATE_POWER;
+ regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
- ah->ah_sc = sc;
ah->hw_version.magic = AR5416_MAGIC;
- ah->regulatory.country_code = CTRY_DEFAULT;
- ah->hw_version.devid = devid;
ah->hw_version.subvendorid = 0;
ah->ah_flags = 0;
- if ((devid == AR5416_AR9100_DEVID))
+ if (ah->hw_version.devid == AR5416_AR9100_DEVID)
ah->hw_version.macVersion = AR_SREV_VERSION_9100;
if (!AR_SREV_9100(ah))
ah->ah_flags = AH_USE_EEPROM;
- ah->regulatory.power_limit = MAX_RATE_POWER;
- ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
ah->atim_window = 0;
- ah->diversity_control = ah->config.diversity_control;
- ah->antenna_switch_swap =
- ah->config.antenna_switch_swap;
ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
ah->beacon_interval = 100;
ah->enable_32kHz_clock = DONT_USE_32KHZ;
ah->gbeacon_rate = 0;
ah->power_mode = ATH9K_PM_UNDEFINED;
-
- return ah;
}
static int ath9k_hw_rfattach(struct ath_hw *ah)
}
}
-static int ath9k_hw_post_attach(struct ath_hw *ah)
+static int ath9k_hw_post_init(struct ath_hw *ah)
{
int ecode;
if (ecode != 0)
return ecode;
- ecode = ath9k_hw_eeprom_attach(ah);
+ ecode = ath9k_hw_eeprom_init(ah);
if (ecode != 0)
return ecode;
if (!AR_SREV_9100(ah)) {
ath9k_hw_ani_setup(ah);
- ath9k_hw_ani_attach(ah);
+ ath9k_hw_ani_init(ah);
}
return 0;
}
-static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
- int *status)
+static bool ath9k_hw_devid_supported(u16 devid)
{
- struct ath_hw *ah;
- int ecode;
- u32 i, j;
-
- ah = ath9k_hw_newstate(devid, sc, status);
- if (ah == NULL)
- return NULL;
-
- ath9k_hw_set_defaults(ah);
-
- if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
- DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
- ecode = -EIO;
- goto bad;
- }
-
- if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
- DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
- ecode = -EIO;
- goto bad;
- }
-
- if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
- if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
- (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
- ah->config.serialize_regmode =
- SER_REG_MODE_ON;
- } else {
- ah->config.serialize_regmode =
- SER_REG_MODE_OFF;
- }
+ switch (devid) {
+ case AR5416_DEVID_PCI:
+ case AR5416_DEVID_PCIE:
+ case AR5416_AR9100_DEVID:
+ case AR9160_DEVID_PCI:
+ case AR9280_DEVID_PCI:
+ case AR9280_DEVID_PCIE:
+ case AR9285_DEVID_PCIE:
+ case AR5416_DEVID_AR9287_PCI:
+ case AR5416_DEVID_AR9287_PCIE:
+ return true;
+ default:
+ break;
}
+ return false;
+}
- DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
- ah->config.serialize_regmode);
-
- switch (ah->hw_version.macVersion) {
+static bool ath9k_hw_macversion_supported(u32 macversion)
+{
+ switch (macversion) {
case AR_SREV_VERSION_5416_PCI:
case AR_SREV_VERSION_5416_PCIE:
case AR_SREV_VERSION_9160:
case AR_SREV_VERSION_9280:
case AR_SREV_VERSION_9285:
case AR_SREV_VERSION_9287:
- break;
+ return true;
+ /* Not yet */
+ case AR_SREV_VERSION_9271:
default:
- DPRINTF(sc, ATH_DBG_FATAL,
- "Mac Chip Rev 0x%02x.%x is not supported by "
- "this driver\n", ah->hw_version.macVersion,
- ah->hw_version.macRev);
- ecode = -EOPNOTSUPP;
- goto bad;
- }
-
- if (AR_SREV_9100(ah)) {
- ah->iq_caldata.calData = &iq_cal_multi_sample;
- ah->supp_cals = IQ_MISMATCH_CAL;
- ah->is_pciexpress = false;
+ break;
}
- ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
+ return false;
+}
+static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
+{
if (AR_SREV_9160_10_OR_LATER(ah)) {
if (AR_SREV_9280_10_OR_LATER(ah)) {
ah->iq_caldata.calData = &iq_cal_single_sample;
}
ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
}
+}
+
+static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
+{
+ if (AR_SREV_9271(ah)) {
+ INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
+ ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
+ INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
+ ARRAY_SIZE(ar9271Common_9271_1_0), 2);
+ return;
+ }
- ah->ani_function = ATH9K_ANI_ALL;
- if (AR_SREV_9280_10_OR_LATER(ah))
- ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
if (AR_SREV_9287_11_OR_LATER(ah)) {
INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
ARRAY_SIZE(ar5416Addac), 2);
}
+}
- if (ah->is_pciexpress)
- ath9k_hw_configpcipowersave(ah, 0);
- else
- ath9k_hw_disablepcie(ah);
-
- ecode = ath9k_hw_post_attach(ah);
- if (ecode != 0)
- goto bad;
-
+static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
+{
if (AR_SREV_9287_11(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9287Modes_rx_gain_9287_1_1,
}
}
+}
- ath9k_hw_fill_cap_info(ah);
+static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
+{
+ u32 i, j;
if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
}
}
}
+}
+
+int ath9k_hw_init(struct ath_hw *ah)
+{
+ int r = 0;
+
+ if (!ath9k_hw_devid_supported(ah->hw_version.devid))
+ return -EOPNOTSUPP;
+
+ ath9k_hw_init_defaults(ah);
+ ath9k_hw_init_config(ah);
+
+ if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
+ DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
+ return -EIO;
+ }
+
+ if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
+ DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
+ return -EIO;
+ }
+
+ if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
+ if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
+ (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
+ ah->config.serialize_regmode =
+ SER_REG_MODE_ON;
+ } else {
+ ah->config.serialize_regmode =
+ SER_REG_MODE_OFF;
+ }
+ }
- ecode = ath9k_hw_init_macaddr(ah);
- if (ecode != 0) {
- DPRINTF(sc, ATH_DBG_FATAL,
+ DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
+ ah->config.serialize_regmode);
+
+ if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
+ DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
+ "Mac Chip Rev 0x%02x.%x is not supported by "
+ "this driver\n", ah->hw_version.macVersion,
+ ah->hw_version.macRev);
+ return -EOPNOTSUPP;
+ }
+
+ if (AR_SREV_9100(ah)) {
+ ah->iq_caldata.calData = &iq_cal_multi_sample;
+ ah->supp_cals = IQ_MISMATCH_CAL;
+ ah->is_pciexpress = false;
+ }
+
+ if (AR_SREV_9271(ah))
+ ah->is_pciexpress = false;
+
+ ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
+
+ ath9k_hw_init_cal_settings(ah);
+
+ ah->ani_function = ATH9K_ANI_ALL;
+ if (AR_SREV_9280_10_OR_LATER(ah))
+ ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
+
+ ath9k_hw_init_mode_regs(ah);
+
+ if (ah->is_pciexpress)
+ ath9k_hw_configpcipowersave(ah, 0);
+ else
+ ath9k_hw_disablepcie(ah);
+
+ r = ath9k_hw_post_init(ah);
+ if (r)
+ return r;
+
+ ath9k_hw_init_mode_gain_regs(ah);
+ ath9k_hw_fill_cap_info(ah);
+ ath9k_hw_init_11a_eeprom_fix(ah);
+
+ r = ath9k_hw_init_macaddr(ah);
+ if (r) {
+ DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Failed to initialize MAC address\n");
- goto bad;
+ return r;
}
- if (AR_SREV_9285(ah))
+ if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
else
ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
ath9k_init_nfcal_hist_buffer(ah);
- return ah;
-bad:
- if (ah)
- ath9k_hw_detach(ah);
- if (status)
- *status = ecode;
-
- return NULL;
+ return 0;
}
static void ath9k_hw_init_bb(struct ath_hw *ah,
void ath9k_hw_detach(struct ath_hw *ah)
{
if (!AR_SREV_9100(ah))
- ath9k_hw_ani_detach(ah);
+ ath9k_hw_ani_disable(ah);
- ath9k_hw_rfdetach(ah);
+ ath9k_hw_rf_free(ah);
ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
kfree(ah);
-}
-
-struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
-{
- struct ath_hw *ah = NULL;
-
- switch (devid) {
- case AR5416_DEVID_PCI:
- case AR5416_DEVID_PCIE:
- case AR5416_AR9100_DEVID:
- case AR9160_DEVID_PCI:
- case AR9280_DEVID_PCI:
- case AR9280_DEVID_PCIE:
- case AR9285_DEVID_PCIE:
- case AR5416_DEVID_AR9287_PCI:
- case AR5416_DEVID_AR9287_PCIE:
- ah = ath9k_hw_do_attach(devid, sc, error);
- break;
- default:
- *error = -ENXIO;
- break;
- }
-
- return ah;
+ ah = NULL;
}
/*******/
static void ath9k_hw_override_ini(struct ath_hw *ah,
struct ath9k_channel *chan)
{
+ u32 val;
+
+ if (AR_SREV_9271(ah)) {
+ /*
+ * Enable spectral scan to solution for issues with stuck
+ * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
+ * AR9271 1.1
+ */
+ if (AR_SREV_9271_10(ah)) {
+ val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
+ REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
+ }
+ else if (AR_SREV_9271_11(ah))
+ /*
+ * change AR_PHY_RF_CTL3 setting to fix MAC issue
+ * present on AR9271 1.1
+ */
+ REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
+ return;
+ }
+
/*
* Set the RX_ABORT and RX_DIS and clear if off only after
* RXE is set for MAC. This prevents frames with corrupted
if (!AR_SREV_5416_20_OR_LATER(ah) ||
AR_SREV_9280_10_OR_LATER(ah))
return;
-
+ /*
+ * Disable BB clock gating
+ * Necessary to avoid issues on AR5416 2.0
+ */
REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
}
{
u32 i;
- for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
- ah->originalGain[i] =
- MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
- AR_PHY_TX_GAIN);
- ah->PDADCdelta = 0;
+ if (OLC_FOR_AR9287_10_LATER) {
+ REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
+ AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
+ ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
+ AR9287_AN_TXPC0_TXPCMODE,
+ AR9287_AN_TXPC0_TXPCMODE_S,
+ AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
+ udelay(100);
+ } else {
+ for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
+ ah->originalGain[i] =
+ MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
+ AR_PHY_TX_GAIN);
+ ah->PDADCdelta = 0;
+ }
}
static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
struct ath9k_channel *chan,
enum ath9k_ht_macmode macmode)
{
+ struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
int i, regWrites = 0;
struct ieee80211_channel *channel = chan->chan;
u32 modesIndex, freqIndex;
ath9k_olc_init(ah);
ah->eep_ops->set_txpower(ah, chan,
- ath9k_regd_get_ctl(&ah->regulatory, chan),
+ ath9k_regd_get_ctl(regulatory, chan),
channel->max_antenna_gain * 2,
channel->max_power * 2,
min((u32) MAX_RATE_POWER,
- (u32) ah->regulatory.power_limit));
+ (u32) regulatory->power_limit));
if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
{
u32 regval;
+ /*
+ * set AHB_MODE not to do cacheline prefetches
+ */
regval = REG_READ(ah, AR_AHB_MODE);
REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
+ /*
+ * let mac dma reads be in 128 byte chunks
+ */
regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
+ /*
+ * Restore TX Trigger Level to its pre-reset value.
+ * The initial value depends on whether aggregation is enabled, and is
+ * adjusted whenever underruns are detected.
+ */
REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
+ /*
+ * let mac dma writes be in 128 byte chunks
+ */
regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
+ /*
+ * Setup receive FIFO threshold to hold off TX activities
+ */
REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
+ /*
+ * reduce the number of usable entries in PCU TXBUF to avoid
+ * wrap around issues.
+ */
if (AR_SREV_9285(ah)) {
+ /* For AR9285 the number of Fifos are reduced to half.
+ * So set the usable tx buf size also to half to
+ * avoid data/delimiter underruns
+ */
REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
- } else {
+ } else if (!AR_SREV_9271(ah)) {
REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
AR_PCU_TXBUF_CTRL_USABLE_SIZE);
}
REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
AR_RTC_FORCE_WAKE_ON_INT);
+ if (!AR_SREV_9100(ah))
+ REG_WRITE(ah, AR_RC, AR_RC_AHB);
+
REG_WRITE(ah, AR_RTC_RESET, 0);
udelay(2);
+
+ if (!AR_SREV_9100(ah))
+ REG_WRITE(ah, AR_RC, 0);
+
REG_WRITE(ah, AR_RTC_RESET, 1);
if (!ath9k_hw_wait(ah,
struct ath9k_channel *chan,
enum ath9k_ht_macmode macmode)
{
+ struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ieee80211_channel *channel = chan->chan;
u32 synthDelay, qnum;
}
ah->eep_ops->set_txpower(ah, chan,
- ath9k_regd_get_ctl(&ah->regulatory, chan),
+ ath9k_regd_get_ctl(regulatory, chan),
channel->max_antenna_gain * 2,
channel->max_power * 2,
min((u32) MAX_RATE_POWER,
- (u32) ah->regulatory.power_limit));
+ (u32) regulatory->power_limit));
synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
if (IS_CHAN_B(chan))
ath9k_hw_mark_phy_inactive(ah);
+ if (AR_SREV_9271(ah) && ah->htc_reset_init) {
+ REG_WRITE(ah,
+ AR9271_RESET_POWER_DOWN_CONTROL,
+ AR9271_RADIO_RF_RST);
+ udelay(50);
+ }
+
if (!ath9k_hw_chip_reset(ah, chan)) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
return -EINVAL;
}
+ if (AR_SREV_9271(ah) && ah->htc_reset_init) {
+ ah->htc_reset_init = false;
+ REG_WRITE(ah,
+ AR9271_RESET_POWER_DOWN_CONTROL,
+ AR9271_GATE_MAC_CTL);
+ udelay(50);
+ }
+
if (AR_SREV_9280_10_OR_LATER(ah))
REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
- if (AR_SREV_9287_10_OR_LATER(ah)) {
+ if (AR_SREV_9287_12_OR_LATER(ah)) {
/* Enable ASYNC FIFO */
REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
ath9k_hw_init_user_settings(ah);
- if (AR_SREV_9287_10_OR_LATER(ah)) {
+ if (AR_SREV_9287_12_OR_LATER(ah)) {
REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
}
- if (AR_SREV_9287_10_OR_LATER(ah)) {
+ if (AR_SREV_9287_12_OR_LATER(ah)) {
REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
}
REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
+ /*
+ * For big endian systems turn on swapping for descriptors
+ */
if (AR_SREV_9100(ah)) {
u32 mask;
mask = REG_READ(ah, AR_CFG);
"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
}
} else {
+ /* Configure AR9271 target WLAN */
+ if (AR_SREV_9271(ah))
+ REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
#ifdef __BIG_ENDIAN
- REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
+ else
+ REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
#endif
}
+ if (ah->ah_sc->sc_flags & SC_OP_BTCOEX_ENABLED)
+ ath9k_hw_btcoex_enable(ah);
+
return 0;
}
}
- if (ah->curchan == NULL)
- return true;
-
return true;
}
/*
* AR9280 2.0 or later chips use SerDes values from the
* initvals.h initialized depending on chipset during
- * ath9k_hw_do_attach()
+ * ath9k_hw_init()
*/
for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
if (ah->config.pcie_waen) {
REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
} else {
- if (AR_SREV_9285(ah))
+ if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah))
REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
/*
* On AR9280 chips bit 22 of 0x4004 needs to be set to
if (AR_SREV_9100(ah))
return true;
+ if (isr & AR_ISR_GENTMR) {
+ u32 s5_s;
+
+ s5_s = REG_READ(ah, AR_ISR_S5_S);
+ if (isr & AR_ISR_GENTMR) {
+ ah->intr_gen_timer_trigger =
+ MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
+
+ ah->intr_gen_timer_thresh =
+ MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
+
+ if (ah->intr_gen_timer_trigger)
+ *masked |= ATH9K_INT_GENTIMER;
+
+ }
+ }
+
if (sync_cause) {
fatal_int =
(sync_cause &
void ath9k_hw_fill_cap_info(struct ath_hw *ah)
{
struct ath9k_hw_capabilities *pCap = &ah->caps;
+ struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+ struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
+
u16 capField = 0, eeval;
eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
- ah->regulatory.current_rd = eeval;
+ regulatory->current_rd = eeval;
eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
if (AR_SREV_9285_10_OR_LATER(ah))
eeval |= AR9285_RDEXT_DEFAULT;
- ah->regulatory.current_rd_ext = eeval;
+ regulatory->current_rd_ext = eeval;
capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
if (ah->opmode != NL80211_IFTYPE_AP &&
ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
- if (ah->regulatory.current_rd == 0x64 ||
- ah->regulatory.current_rd == 0x65)
- ah->regulatory.current_rd += 5;
- else if (ah->regulatory.current_rd == 0x41)
- ah->regulatory.current_rd = 0x43;
+ if (regulatory->current_rd == 0x64 ||
+ regulatory->current_rd == 0x65)
+ regulatory->current_rd += 5;
+ else if (regulatory->current_rd == 0x41)
+ regulatory->current_rd = 0x43;
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
- "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
+ "regdomain mapped to 0x%x\n", regulatory->current_rd);
}
eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
}
pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
+ /*
+ * For AR9271 we will temporarilly uses the rx chainmax as read from
+ * the EEPROM.
+ */
if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
- !(eeval & AR5416_OPFLAGS_11A))
+ !(eeval & AR5416_OPFLAGS_11A) &&
+ !(AR_SREV_9271(ah)))
+ /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
else
+ /* Use rx_chainmask from EEPROM. */
pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
else
pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
- if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
+ if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
pCap->reg_cap =
AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
- pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
- ah->btactive_gpio = 6;
- ah->wlanactive_gpio = 5;
+ btcoex_info->btactive_gpio = ATH_BTACTIVE_GPIO;
+ btcoex_info->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
+
+ if (AR_SREV_9285(ah))
+ btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_3WIRE;
+ else
+ btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_2WIRE;
+ } else {
+ btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_NONE;
}
}
bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
u32 capability, u32 *result)
{
+ struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
switch (type) {
case ATH9K_CAP_CIPHER:
switch (capability) {
case 0:
return 0;
case 1:
- *result = ah->regulatory.power_limit;
+ *result = regulatory->power_limit;
return 0;
case 2:
- *result = ah->regulatory.max_power_level;
+ *result = regulatory->max_power_level;
return 0;
case 3:
- *result = ah->regulatory.tp_scale;
+ *result = regulatory->tp_scale;
return 0;
}
return false;
break;
}
} else {
- ah->diversity_control = settings;
+ ah->config.diversity_control = settings;
}
return true;
{
u32 phybits;
- REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
+ REG_WRITE(ah, AR_RX_FILTER, bits);
+
phybits = 0;
if (bits & ATH9K_RX_FILTER_PHYRADAR)
phybits |= AR_PHY_ERR_RADAR;
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
{
+ struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ath9k_channel *chan = ah->curchan;
struct ieee80211_channel *channel = chan->chan;
- ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
+ regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
ah->eep_ops->set_txpower(ah, chan,
- ath9k_regd_get_ctl(&ah->regulatory, chan),
+ ath9k_regd_get_ctl(regulatory, chan),
channel->max_antenna_gain * 2,
channel->max_power * 2,
min((u32) MAX_RATE_POWER,
- (u32) ah->regulatory.power_limit));
+ (u32) regulatory->power_limit));
}
void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
ath9k_ps_restore(ah->ah_sc);
}
-bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
+void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
{
if (setting)
ah->misc_mode |= AR_PCU_TX_ADD_TSF;
else
ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
-
- return true;
}
bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
REG_WRITE(ah, AR_2040_MODE, macmode);
}
-/***************************/
-/* Bluetooth Coexistence */
-/***************************/
+/* HW Generic timers configuration */
-void ath9k_hw_btcoex_enable(struct ath_hw *ah)
+static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
+{
+ {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+ {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+ {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+ {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+ {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+ {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+ {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+ {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+ {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
+ {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
+ AR_NDP2_TIMER_MODE, 0x0002},
+ {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
+ AR_NDP2_TIMER_MODE, 0x0004},
+ {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
+ AR_NDP2_TIMER_MODE, 0x0008},
+ {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
+ AR_NDP2_TIMER_MODE, 0x0010},
+ {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
+ AR_NDP2_TIMER_MODE, 0x0020},
+ {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
+ AR_NDP2_TIMER_MODE, 0x0040},
+ {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
+ AR_NDP2_TIMER_MODE, 0x0080}
+};
+
+/* HW generic timer primitives */
+
+/* compute and clear index of rightmost 1 */
+static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
{
- /* connect bt_active to baseband */
- REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
- (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
- AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
+ u32 b;
- REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
- AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
+ b = *mask;
+ b &= (0-b);
+ *mask &= ~b;
+ b *= debruijn32;
+ b >>= 27;
+
+ return timer_table->gen_timer_index[b];
+}
+
+u32 ath9k_hw_gettsf32(struct ath_hw *ah)
+{
+ return REG_READ(ah, AR_TSF_L32);
+}
+
+struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
+ void (*trigger)(void *),
+ void (*overflow)(void *),
+ void *arg,
+ u8 timer_index)
+{
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+ struct ath_gen_timer *timer;
+
+ timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
+
+ if (timer == NULL) {
+ printk(KERN_DEBUG "Failed to allocate memory"
+ "for hw timer[%d]\n", timer_index);
+ return NULL;
+ }
+
+ /* allocate a hardware generic timer slot */
+ timer_table->timers[timer_index] = timer;
+ timer->index = timer_index;
+ timer->trigger = trigger;
+ timer->overflow = overflow;
+ timer->arg = arg;
+
+ return timer;
+}
+
+void ath_gen_timer_start(struct ath_hw *ah,
+ struct ath_gen_timer *timer,
+ u32 timer_next, u32 timer_period)
+{
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+ u32 tsf;
+
+ BUG_ON(!timer_period);
+
+ set_bit(timer->index, &timer_table->timer_mask.timer_bits);
+
+ tsf = ath9k_hw_gettsf32(ah);
+
+ DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, "curent tsf %x period %x"
+ "timer_next %x\n", tsf, timer_period, timer_next);
+
+ /*
+ * Pull timer_next forward if the current TSF already passed it
+ * because of software latency
+ */
+ if (timer_next < tsf)
+ timer_next = tsf + timer_period;
+
+ /*
+ * Program generic timer registers
+ */
+ REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
+ timer_next);
+ REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
+ timer_period);
+ REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
+ gen_tmr_configuration[timer->index].mode_mask);
+
+ /* Enable both trigger and thresh interrupt masks */
+ REG_SET_BIT(ah, AR_IMR_S5,
+ (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
+ SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
+
+ if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
+ ath9k_hw_set_interrupts(ah, 0);
+ ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
+ ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
+ }
+}
+
+void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
+{
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
- /* Set input mux for bt_active to gpio pin */
- REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
- AR_GPIO_INPUT_MUX1_BT_ACTIVE,
- ah->btactive_gpio);
+ if ((timer->index < AR_FIRST_NDP_TIMER) ||
+ (timer->index >= ATH_MAX_GEN_TIMER)) {
+ return;
+ }
+
+ /* Clear generic timer enable bits. */
+ REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
+ gen_tmr_configuration[timer->index].mode_mask);
+
+ /* Disable both trigger and thresh interrupt masks */
+ REG_CLR_BIT(ah, AR_IMR_S5,
+ (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
+ SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
+
+ clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
- /* Configure the desired gpio port for input */
- ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
+ /* if no timer is enabled, turn off interrupt mask */
+ if (timer_table->timer_mask.val == 0) {
+ ath9k_hw_set_interrupts(ah, 0);
+ ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
+ ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
+ }
+}
+
+void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
+{
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
- /* Configure the desired GPIO port for TX_FRAME output */
- ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
- AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
+ /* free the hardware generic timer slot */
+ timer_table->timers[timer->index] = NULL;
+ kfree(timer);
+}
+
+/*
+ * Generic Timer Interrupts handling
+ */
+void ath_gen_timer_isr(struct ath_hw *ah)
+{
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+ struct ath_gen_timer *timer;
+ u32 trigger_mask, thresh_mask, index;
+
+ /* get hardware generic timer interrupt status */
+ trigger_mask = ah->intr_gen_timer_trigger;
+ thresh_mask = ah->intr_gen_timer_thresh;
+ trigger_mask &= timer_table->timer_mask.val;
+ thresh_mask &= timer_table->timer_mask.val;
+
+ trigger_mask &= ~thresh_mask;
+
+ while (thresh_mask) {
+ index = rightmost_index(timer_table, &thresh_mask);
+ timer = timer_table->timers[index];
+ BUG_ON(!timer);
+ DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
+ "TSF overflow for Gen timer %d\n", index);
+ timer->overflow(timer->arg);
+ }
+
+ while (trigger_mask) {
+ index = rightmost_index(timer_table, &trigger_mask);
+ timer = timer_table->timers[index];
+ BUG_ON(!timer);
+ DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
+ "Gen timer[%d] trigger\n", index);
+ timer->trigger(timer->arg);
+ }
}
projects / firefly-linux-kernel-4.4.55.git / blobdiff