u32 adv_ts;
int use_riwt;
spinlock_t ptp_lock;
+ bool mdio_registered;
+};
+
+enum {
+ RK3288_GMAC,
+ RK312X_GMAC,
+ RK3368_GMAC
};
struct bsp_priv {
- char pwr_ctl_by[8];
+ struct regmap *grf;
+ struct platform_device *pdev;
+ bool power_ctrl_by_pmu;
+ char pmu_regulator[32];
int power_io;
int power_io_level;
int reset_io;
int reset_io_level;
+ int phyirq_io;
+ int phyirq_io_level;
int phy_iface;
- int (*phy_power_on)(struct plat_stmmacenet_data *plat, int enable);
+ bool clock_input;
+ int chip;
+ int tx_delay;
+ int rx_delay;
+
+ struct clk *clk_mac;
+ struct clk *clk_mac_pll;
+ struct clk *gmac_clkin;
+ struct clk *mac_clk_rx;
+ struct clk *mac_clk_tx;
+ struct clk *clk_mac_ref;
+ struct clk *clk_mac_refout;
+ struct clk *aclk_mac;
+ struct clk *pclk_mac;
+ bool clk_enable;
+
+ int (*phy_power_on)(bool enable);
+ int (*gmac_clk_enable)(bool enable);
};
extern int phyaddr;