/*******************************************************************************
Intel PRO/1000 Linux driver
- Copyright(c) 1999 - 2011 Intel Corporation.
+ Copyright(c) 1999 - 2012 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
#define I82579_EMI_ADDR 0x10
#define I82579_EMI_DATA 0x11
#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
+#define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */
+#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
/* Strapping Option Register - RO */
#define E1000_STRAP 0x0000C
#define er16flash(reg) __er16flash(hw, (reg))
#define er32flash(reg) __er32flash(hw, (reg))
-#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
-#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
+#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
+#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
{
static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
- u32 fwsm;
s32 ret_val = 0;
phy->addr = 1;
phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- /*
- * The MAC-PHY interconnect may still be in SMBus mode
- * after Sx->S0. If the manageability engine (ME) is
- * disabled, then toggle the LANPHYPC Value bit to force
- * the interconnect to PCIe mode.
- */
- fwsm = er32(FWSM);
- if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
+ if (!e1000_check_reset_block(hw)) {
+ u32 fwsm = er32(FWSM);
+
+ /*
+ * The MAC-PHY interconnect may still be in SMBus mode after
+ * Sx->S0. If resetting the PHY is not blocked, toggle the
+ * LANPHYPC Value bit to force the interconnect to PCIe mode.
+ */
e1000_toggle_lanphypc_value_ich8lan(hw);
msleep(50);
* Gate automatic PHY configuration by hardware on
* non-managed 82579
*/
- if (hw->mac.type == e1000_pch2lan)
+ if ((hw->mac.type == e1000_pch2lan) &&
+ !(fwsm & E1000_ICH_FWSM_FW_VALID))
e1000_gate_hw_phy_config_ich8lan(hw, true);
- }
- /*
- * Reset the PHY before any access to it. Doing so, ensures that
- * the PHY is in a known good state before we read/write PHY registers.
- * The generic reset is sufficient here, because we haven't determined
- * the PHY type yet.
- */
- ret_val = e1000e_phy_hw_reset_generic(hw);
- if (ret_val)
- goto out;
+ /*
+ * Reset the PHY before any access to it. Doing so, ensures
+ * that the PHY is in a known good state before we read/write
+ * PHY registers. The generic reset is sufficient here,
+ * because we haven't determined the PHY type yet.
+ */
+ ret_val = e1000e_phy_hw_reset_generic(hw);
+ if (ret_val)
+ goto out;
- /* Ungate automatic PHY configuration on non-managed 82579 */
- if ((hw->mac.type == e1000_pch2lan) &&
- !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
- usleep_range(10000, 20000);
- e1000_gate_hw_phy_config_ich8lan(hw, false);
+ /* Ungate automatic PHY configuration on non-managed 82579 */
+ if ((hw->mac.type == e1000_pch2lan) &&
+ !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
+ usleep_range(10000, 20000);
+ e1000_gate_hw_phy_config_ich8lan(hw, false);
+ }
}
phy->id = e1000_phy_unknown;
* Initialize family-specific MAC parameters and function
* pointers.
**/
-static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
+static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
{
- struct e1000_hw *hw = &adapter->hw;
struct e1000_mac_info *mac = &hw->mac;
/* Set media type function pointer */
struct e1000_hw *hw = &adapter->hw;
s32 rc;
- rc = e1000_init_mac_params_ich8lan(adapter);
+ rc = e1000_init_mac_params_ich8lan(hw);
if (rc)
return rc;
}
if (!timeout) {
- e_dbg("Failed to acquire the semaphore, FW or HW has it: "
- "FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
+ e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
er32(FWSM), extcnf_ctrl);
extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
ew32(EXTCNF_CTRL, extcnf_ctrl);
data = er32(FEXTNVM);
if (!(data & sw_cfg_mask))
- goto out;
+ goto release;
/*
* Make sure HW does not configure LCD from PHY
data = er32(EXTCNF_CTRL);
if (!(hw->mac.type == e1000_pch2lan)) {
if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
- goto out;
+ goto release;
}
cnf_size = er32(EXTCNF_SIZE);
cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
if (!cnf_size)
- goto out;
+ goto release;
cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
*/
ret_val = e1000_write_smbus_addr(hw);
if (ret_val)
- goto out;
+ goto release;
data = er32(LEDCTL);
ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
(u16)data);
if (ret_val)
- goto out;
+ goto release;
}
/* Configure LCD from extended configuration region. */
ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
®_data);
if (ret_val)
- goto out;
+ goto release;
ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1, ®_addr);
if (ret_val)
- goto out;
+ goto release;
/* Save off the PHY page for future writes. */
if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
reg_data);
if (ret_val)
- goto out;
+ goto release;
}
-out:
+release:
hw->phy.ops.release(hw);
return ret_val;
}
if (!(hw->mac.type == e1000_pch2lan)) {
mac_reg = er32(EXTCNF_CTRL);
if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
- goto out;
+ goto release;
}
mac_reg = er32(FEXTNVM);
if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
- goto out;
+ goto release;
mac_reg = er32(PHY_CTRL);
ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
if (ret_val)
- goto out;
+ goto release;
oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
-out:
+release:
hw->phy.ops.release(hw);
return ret_val;
/* Set MDIO slow mode before any other MDIO access */
ret_val = e1000_set_mdio_slow_mode_hv(hw);
+ ret_val = hw->phy.ops.acquire(hw);
+ if (ret_val)
+ goto out;
+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
+ I82579_MSE_THRESHOLD);
+ if (ret_val)
+ goto release;
+ /* set MSE higher to enable link to stay up when noise is high */
+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0034);
+ if (ret_val)
+ goto release;
+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
+ I82579_MSE_LINK_DOWN);
+ if (ret_val)
+ goto release;
+ /* drop link after 5 times MSE threshold was reached */
+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0005);
+release:
+ hw->phy.ops.release(hw);
+
out:
return ret_val;
}
extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
ew32(EXTCNF_CTRL, extcnf_ctrl);
- return;
}
/**
else
oem_reg &= ~HV_OEM_BITS_LPLU;
- oem_reg |= HV_OEM_BITS_RESTART_AN;
+ if (!e1000_check_reset_block(hw))
+ oem_reg |= HV_OEM_BITS_RESTART_AN;
+
ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
out:
u16 data;
if (phy->type == e1000_phy_ife)
- return ret_val;
+ return 0;
phy_ctrl = er32(PHY_CTRL);
{
struct e1000_phy_info *phy = &hw->phy;
u32 phy_ctrl;
- s32 ret_val;
+ s32 ret_val = 0;
u16 data;
phy_ctrl = er32(PHY_CTRL);
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
}
- return 0;
+ return ret_val;
}
/**
return 0;
}
- e_dbg("Unable to determine valid NVM bank via EEC - "
- "reading flash signature\n");
+ e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
/* fall-thru */
default:
/* set bank to 0 in case flash read fails */
e_dbg("ERROR: No valid NVM bank present\n");
return -E1000_ERR_NVM;
}
-
- return 0;
}
/**
/* Check if the flash descriptor is valid */
if (hsfsts.hsf_status.fldesvalid == 0) {
- e_dbg("Flash descriptor invalid. "
- "SW Sequencing must be used.\n");
+ e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
return -E1000_ERR_NVM;
}
* cycle has a chance to end before giving up.
*/
for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
- hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
+ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
if (hsfsts.hsf_status.flcinprog == 0) {
ret_val = 0;
break;
}
udelay(1);
}
- if (ret_val == 0) {
+ if (!ret_val) {
/*
* Successful in waiting for previous cycle to timeout,
* now set the Flash Cycle Done.
udelay(1);
/* Steps */
ret_val = e1000_flash_cycle_init_ich8lan(hw);
- if (ret_val != 0)
+ if (ret_val)
break;
hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
* read in (shift in) the Flash Data0, the order is
* least significant byte first msb to lsb
*/
- if (ret_val == 0) {
+ if (!ret_val) {
flash_data = er32flash(ICH_FLASH_FDATA0);
if (size == 1)
*data = (u8)(flash_data & 0x000000FF);
/* Repeat for some time before giving up. */
continue;
} else if (hsfsts.hsf_status.flcdone == 0) {
- e_dbg("Timeout error - flash cycle "
- "did not complete.\n");
+ e_dbg("Timeout error - flash cycle did not complete.\n");
break;
}
}
/* Repeat for some time before giving up. */
continue;
if (hsfsts.hsf_status.flcdone == 0) {
- e_dbg("Timeout error - flash cycle "
- "did not complete.");
+ e_dbg("Timeout error - flash cycle did not complete.\n");
break;
}
} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
ret_val = e1000_flash_cycle_ich8lan(hw,
ICH_FLASH_ERASE_COMMAND_TIMEOUT);
- if (ret_val == 0)
+ if (!ret_val)
break;
/*
*
* During S0 to Sx transition, it is possible the link remains at gig
* instead of negotiating to a lower speed. Before going to Sx, set
- * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
- * to a lower speed. For PCH and newer parts, the OEM bits PHY register
- * (LED, GbE disable and LPLU configurations) also needs to be written.
+ * 'Gig Disable' to force link speed negotiation to a lower speed based on
+ * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
+ * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
+ * needs to be written.
**/
void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
{
s32 ret_val;
phy_ctrl = er32(PHY_CTRL);
- phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
+ phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
ew32(PHY_CTRL, phy_ctrl);
if (hw->mac.type == e1000_ich8lan)
**/
void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
{
- u32 fwsm;
+ u16 phy_id1, phy_id2;
+ s32 ret_val;
- if (hw->mac.type != e1000_pch2lan)
+ if ((hw->mac.type != e1000_pch2lan) || e1000_check_reset_block(hw))
return;
- fwsm = er32(FWSM);
- if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
- u16 phy_id1, phy_id2;
- s32 ret_val;
-
- ret_val = hw->phy.ops.acquire(hw);
- if (ret_val) {
- e_dbg("Failed to acquire PHY semaphore in resume\n");
- return;
- }
+ ret_val = hw->phy.ops.acquire(hw);
+ if (ret_val) {
+ e_dbg("Failed to acquire PHY semaphore in resume\n");
+ return;
+ }
- /* Test access to the PHY registers by reading the ID regs */
- ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
- if (ret_val)
- goto release;
- ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
- if (ret_val)
- goto release;
+ /* Test access to the PHY registers by reading the ID regs */
+ ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
+ if (ret_val)
+ goto release;
+ ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
+ if (ret_val)
+ goto release;
- if (hw->phy.id == ((u32)(phy_id1 << 16) |
- (u32)(phy_id2 & PHY_REVISION_MASK)))
- goto release;
+ if (hw->phy.id == ((u32)(phy_id1 << 16) |
+ (u32)(phy_id2 & PHY_REVISION_MASK)))
+ goto release;
- e1000_toggle_lanphypc_value_ich8lan(hw);
+ e1000_toggle_lanphypc_value_ich8lan(hw);
- hw->phy.ops.release(hw);
- msleep(50);
- e1000_phy_hw_reset(hw);
- msleep(50);
- return;
- }
+ hw->phy.ops.release(hw);
+ msleep(50);
+ e1000_phy_hw_reset(hw);
+ msleep(50);
+ return;
release:
hw->phy.ops.release(hw);
-
- return;
}
/**
| FLAG_HAS_WOL
| FLAG_HAS_CTRLEXT_ON_LOAD
| FLAG_HAS_AMT
- | FLAG_HAS_ERT
| FLAG_HAS_FLASH
| FLAG_APME_IN_WUC,
- .pba = 10,
+ .pba = 18,
.max_hw_frame_size = DEFAULT_JUMBO,
.get_variants = e1000_get_variants_ich8lan,
.mac_ops = &ich8_mac_ops,
| FLAG_HAS_WOL
| FLAG_HAS_CTRLEXT_ON_LOAD
| FLAG_HAS_AMT
- | FLAG_HAS_ERT
| FLAG_HAS_FLASH
| FLAG_APME_IN_WUC,
- .pba = 10,
+ .pba = 18,
.max_hw_frame_size = DEFAULT_JUMBO,
.get_variants = e1000_get_variants_ich8lan,
.mac_ops = &ich8_mac_ops,
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