* Required buffer layout:
* |<--hdr-->|<--ext hdr-->|<---dct part---
*/
-void rk3288_vpu_vp8e_assemble_bitstream(struct rk3288_vpu_ctx *ctx,
- struct rk3288_vpu_buf *dst_buf)
+void rk3288_vpu_vp8e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
+ struct rockchip_vpu_buf *dst_buf)
{
struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&dst_buf->vb.vb2_buf);
size_t ext_hdr_size = dst_buf->vp8e.ext_hdr_size;
return round_up(w, MB_DIM) * round_up(h, MB_DIM);
}
-int rk3288_vpu_vp8e_init(struct rk3288_vpu_ctx *ctx)
+int rk3288_vpu_vp8e_init(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
size_t height = ctx->src_fmt.height;
size_t width = ctx->src_fmt.width;
size_t ref_buf_size;
size_t mv_size;
int ret;
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ctrl_buf,
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ctrl_buf,
sizeof(struct rk3288_vpu_vp8e_ctrl_buf));
if (ret) {
vpu_err("failed to allocate ctrl buffer\n");
}
mv_size = DIV_ROUND_UP(width, 16) * DIV_ROUND_UP(height, 16) / 4;
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.mv_buf, mv_size);
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.mv_buf, mv_size);
if (ret) {
vpu_err("failed to allocate MV buffer\n");
goto err_ctrl_buf;
}
ref_buf_size = ref_luma_size(width, height) * 3 / 2;
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ext_buf,
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ext_buf,
2 * ref_buf_size);
if (ret) {
vpu_err("failed to allocate ext buffer\n");
return 0;
err_mv_buf:
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
err_ctrl_buf:
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
return ret;
}
-void rk3288_vpu_vp8e_exit(struct rk3288_vpu_ctx *ctx)
+void rk3288_vpu_vp8e_exit(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ext_buf);
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ext_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
}
-static inline u32 enc_in_img_ctrl(struct rk3288_vpu_ctx *ctx)
+static inline u32 enc_in_img_ctrl(struct rockchip_vpu_ctx *ctx)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
struct v4l2_rect *crop = &ctx->src_crop;
| VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
}
-static void rk3288_vpu_vp8e_set_buffers(struct rk3288_vpu_dev *vpu,
- struct rk3288_vpu_ctx *ctx)
+static void rk3288_vpu_vp8e_set_buffers(struct rockchip_vpu_dev *vpu,
+ struct rockchip_vpu_ctx *ctx)
{
struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&ctx->run.dst->vb.vb2_buf);
- const struct rk3288_vp8e_reg_params *params = ctx->run.vp8e.reg_params;
+ const struct rk3288_vp8e_reg_params *params =
+ (struct rk3288_vp8e_reg_params *)ctx->run.vp8e.reg_params;
dma_addr_t ref_buf_dma, rec_buf_dma;
dma_addr_t stream_dma;
size_t rounded_size;
rec_buf_dma += rounded_size * 3 / 2;
ctx->hw.vp8e.ref_rec_ptr ^= 1;
- if (rk3288_vpu_ctx_is_dummy_encode(ctx)) {
+ if (rockchip_vpu_ctx_is_dummy_encode(ctx)) {
dst_dma = vpu->dummy_encode_dst.dma;
dst_size = vpu->dummy_encode_dst.size;
} else {
VEPU_REG_ADDR_REC_CHROMA);
/* Source buffer. */
- if (rk3288_vpu_ctx_is_dummy_encode(ctx)) {
+ if (rockchip_vpu_ctx_is_dummy_encode(ctx)) {
vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_Y].dma,
VEPU_REG_ADDR_IN_LUMA);
vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_CB].dma,
vepu_write_relaxed(vpu, enc_in_img_ctrl(ctx), VEPU_REG_IN_IMG_CTRL);
}
-static void rk3288_vpu_vp8e_set_params(struct rk3288_vpu_dev *vpu,
- struct rk3288_vpu_ctx *ctx)
+static void rk3288_vpu_vp8e_set_params(struct rockchip_vpu_dev *vpu,
+ struct rockchip_vpu_ctx *ctx)
{
- const struct rk3288_vp8e_reg_params *params = ctx->run.vp8e.reg_params;
+ const struct rk3288_vp8e_reg_params *params =
+ (struct rk3288_vp8e_reg_params *)ctx->run.vp8e.reg_params;
int i;
vepu_write_relaxed(vpu, params->enc_ctrl0, VEPU_REG_ENC_CTRL0);
VEPU_REG_VP8_LOOP_FLT_DELTA(i));
}
-void rk3288_vpu_vp8e_run(struct rk3288_vpu_ctx *ctx)
+void rk3288_vpu_vp8e_run(struct rockchip_vpu_ctx *ctx)
{
struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&ctx->run.dst->vb.vb2_buf);
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
u32 reg;
/* The hardware expects the control buffer to be zeroed. */
/*
* Program the hardware.
*/
- rk3288_vpu_power_on(vpu);
+ rockchip_vpu_power_on(vpu);
vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_VP8,
VEPU_REG_ENC_CTRL);
vepu_write(vpu, reg, VEPU_REG_ENC_CTRL);
}
-void rk3288_vpu_vp8e_done(struct rk3288_vpu_ctx *ctx,
+void rk3288_vpu_vp8e_done(struct rockchip_vpu_ctx *ctx,
enum vb2_buffer_state result)
{
struct rk3288_vpu_vp8e_ctrl_buf *ctrl_buf = ctx->hw.vp8e.ctrl_buf.cpu;
ctx->run.dst->vp8e.ext_hdr_size = ctrl_buf->ext_hdr_size;
ctx->run.dst->vp8e.dct_size = ctrl_buf->dct_size;
- rk3288_vpu_run_done(ctx, result);
+ rockchip_vpu_run_done(ctx, result);
}
/*
* WAR for encoder state corruption after decoding
*/
-static const struct rk3288_vp8e_reg_params dummy_encode_reg_params = {
- /* 00000014 */ .hdr_len = 0x00000000,
- /* 00000038 */ .enc_ctrl = VEPU_REG_ENC_CTRL_KEYFRAME_BIT,
- /* 00000040 */ .enc_ctrl0 = 0x00000000,
- /* 00000044 */ .enc_ctrl1 = 0x00000000,
- /* 00000048 */ .enc_ctrl2 = 0x00040014,
- /* 0000004c */ .enc_ctrl3 = 0x404083c0,
- /* 00000050 */ .enc_ctrl5 = 0x01006bff,
- /* 00000054 */ .enc_ctrl4 = 0x00000039,
- /* 00000058 */ .str_hdr_rem_msb = 0x85848805,
- /* 0000005c */ .str_hdr_rem_lsb = 0x02000000,
- /* 00000064 */ .mad_ctrl = 0x00000000,
- /* 0000006c */ .qp_val = {
- /* 0000006c */ 0x020213b1,
- /* 00000070 */ 0x02825249,
- /* 00000074 */ 0x048409d8,
- /* 00000078 */ 0x03834c30,
- /* 0000007c */ 0x020213b1,
- /* 00000080 */ 0x02825249,
- /* 00000084 */ 0x00340e0d,
- /* 00000088 */ 0x401c1a15,
+static const struct rockchip_reg_params dummy_encode_reg_params = {
+ .rk3288_vp8e = {
+ /* 00000014 */ .hdr_len = 0x00000000,
+ /* 00000038 */ .enc_ctrl = VEPU_REG_ENC_CTRL_KEYFRAME_BIT,
+ /* 00000040 */ .enc_ctrl0 = 0x00000000,
+ /* 00000044 */ .enc_ctrl1 = 0x00000000,
+ /* 00000048 */ .enc_ctrl2 = 0x00040014,
+ /* 0000004c */ .enc_ctrl3 = 0x404083c0,
+ /* 00000050 */ .enc_ctrl5 = 0x01006bff,
+ /* 00000054 */ .enc_ctrl4 = 0x00000039,
+ /* 00000058 */ .str_hdr_rem_msb = 0x85848805,
+ /* 0000005c */ .str_hdr_rem_lsb = 0x02000000,
+ /* 00000064 */ .mad_ctrl = 0x00000000,
+ /* 0000006c */ .qp_val = {
+ /* 0000006c */ 0x020213b1,
+ /* 00000070 */ 0x02825249,
+ /* 00000074 */ 0x048409d8,
+ /* 00000078 */ 0x03834c30,
+ /* 0000007c */ 0x020213b1,
+ /* 00000080 */ 0x02825249,
+ /* 00000084 */ 0x00340e0d,
+ /* 00000088 */ 0x401c1a15,
+ },
+ /* 0000008c */ .bool_enc = 0x00018140,
+ /* 00000090 */ .vp8_ctrl0 = 0x000695c0,
+ /* 00000094 */ .rlc_ctrl = 0x14000000,
+ /* 00000098 */ .mb_ctrl = 0x00000000,
+ /* 000000d4 */ .rgb_yuv_coeff = {
+ /* 000000d4 */ 0x962b4c85,
+ /* 000000d8 */ 0x90901d50,
+ },
+ /* 000000dc */ .rgb_mask_msb = 0x0000b694,
+ /* 000000e0 */ .intra_area_ctrl = 0xffffffff,
+ /* 000000e4 */ .cir_intra_ctrl = 0x00000000,
+ /* 000000f0 */ .first_roi_area = 0xffffffff,
+ /* 000000f4 */ .second_roi_area = 0xffffffff,
+ /* 000000f8 */ .mvc_ctrl = 0x01780000,
+ /* 00000100 */ .intra_penalty = {
+ /* 00000100 */ 0x00010005,
+ /* 00000104 */ 0x00015011,
+ /* 00000108 */ 0x0000c005,
+ /* 0000010c */ 0x00016010,
+ /* 00000110 */ 0x0001a018,
+ /* 00000114 */ 0x00018015,
+ /* 00000118 */ 0x0001d01a,
+ },
+ /* 00000120 */ .seg_qp = {
+ /* 00000120 */ 0x020213b1,
+ /* 00000124 */ 0x02825249,
+ /* 00000128 */ 0x048409d8,
+ /* 0000012c */ 0x03834c30,
+ /* 00000130 */ 0x020213b1,
+ /* 00000134 */ 0x02825249,
+ /* 00000138 */ 0x00340e0d,
+ /* 0000013c */ 0x341c1a15,
+ /* 00000140 */ 0x020213b1,
+ /* 00000144 */ 0x02825249,
+ /* 00000148 */ 0x048409d8,
+ /* 0000014c */ 0x03834c30,
+ /* 00000150 */ 0x020213b1,
+ /* 00000154 */ 0x02825249,
+ /* 00000158 */ 0x00340e0d,
+ /* 0000015c */ 0x341c1a15,
+ /* 00000160 */ 0x020213b1,
+ /* 00000164 */ 0x02825249,
+ /* 00000168 */ 0x048409d8,
+ /* 0000016c */ 0x03834c30,
+ /* 00000170 */ 0x020213b1,
+ /* 00000174 */ 0x02825249,
+ /* 00000178 */ 0x00340e0d,
+ /* 0000017c */ 0x341c1a15,
+ },
+ /* 00000180 */ .dmv_4p_1p_penalty = {
+ /* 00000180 */ 0x00020406,
+ /* 00000184 */ 0x080a0c0e,
+ /* 00000188 */ 0x10121416,
+ /* 0000018c */ 0x181a1c1e,
+ /* 00000190 */ 0x20222426,
+ /* 00000194 */ 0x282a2c2e,
+ /* 00000198 */ 0x30323436,
+ /* 0000019c */ 0x383a3c3e,
+ /* 000001a0 */ 0x40424446,
+ /* 000001a4 */ 0x484a4c4e,
+ /* 000001a8 */ 0x50525456,
+ /* 000001ac */ 0x585a5c5e,
+ /* 000001b0 */ 0x60626466,
+ /* 000001b4 */ 0x686a6c6e,
+ /* 000001b8 */ 0x70727476,
+ /* NOTE: Further 17 registers set to 0. */
+ },
+ /*
+ * NOTE: Following registers all set to 0:
+ * - dmv_qpel_penalty,
+ * - vp8_ctrl1,
+ * - bit_cost_golden,
+ * - loop_flt_delta.
+ */
},
- /* 0000008c */ .bool_enc = 0x00018140,
- /* 00000090 */ .vp8_ctrl0 = 0x000695c0,
- /* 00000094 */ .rlc_ctrl = 0x14000000,
- /* 00000098 */ .mb_ctrl = 0x00000000,
- /* 000000d4 */ .rgb_yuv_coeff = {
- /* 000000d4 */ 0x962b4c85,
- /* 000000d8 */ 0x90901d50,
- },
- /* 000000dc */ .rgb_mask_msb = 0x0000b694,
- /* 000000e0 */ .intra_area_ctrl = 0xffffffff,
- /* 000000e4 */ .cir_intra_ctrl = 0x00000000,
- /* 000000f0 */ .first_roi_area = 0xffffffff,
- /* 000000f4 */ .second_roi_area = 0xffffffff,
- /* 000000f8 */ .mvc_ctrl = 0x01780000,
- /* 00000100 */ .intra_penalty = {
- /* 00000100 */ 0x00010005,
- /* 00000104 */ 0x00015011,
- /* 00000108 */ 0x0000c005,
- /* 0000010c */ 0x00016010,
- /* 00000110 */ 0x0001a018,
- /* 00000114 */ 0x00018015,
- /* 00000118 */ 0x0001d01a,
- },
- /* 00000120 */ .seg_qp = {
- /* 00000120 */ 0x020213b1,
- /* 00000124 */ 0x02825249,
- /* 00000128 */ 0x048409d8,
- /* 0000012c */ 0x03834c30,
- /* 00000130 */ 0x020213b1,
- /* 00000134 */ 0x02825249,
- /* 00000138 */ 0x00340e0d,
- /* 0000013c */ 0x341c1a15,
- /* 00000140 */ 0x020213b1,
- /* 00000144 */ 0x02825249,
- /* 00000148 */ 0x048409d8,
- /* 0000014c */ 0x03834c30,
- /* 00000150 */ 0x020213b1,
- /* 00000154 */ 0x02825249,
- /* 00000158 */ 0x00340e0d,
- /* 0000015c */ 0x341c1a15,
- /* 00000160 */ 0x020213b1,
- /* 00000164 */ 0x02825249,
- /* 00000168 */ 0x048409d8,
- /* 0000016c */ 0x03834c30,
- /* 00000170 */ 0x020213b1,
- /* 00000174 */ 0x02825249,
- /* 00000178 */ 0x00340e0d,
- /* 0000017c */ 0x341c1a15,
- },
- /* 00000180 */ .dmv_4p_1p_penalty = {
- /* 00000180 */ 0x00020406,
- /* 00000184 */ 0x080a0c0e,
- /* 00000188 */ 0x10121416,
- /* 0000018c */ 0x181a1c1e,
- /* 00000190 */ 0x20222426,
- /* 00000194 */ 0x282a2c2e,
- /* 00000198 */ 0x30323436,
- /* 0000019c */ 0x383a3c3e,
- /* 000001a0 */ 0x40424446,
- /* 000001a4 */ 0x484a4c4e,
- /* 000001a8 */ 0x50525456,
- /* 000001ac */ 0x585a5c5e,
- /* 000001b0 */ 0x60626466,
- /* 000001b4 */ 0x686a6c6e,
- /* 000001b8 */ 0x70727476,
- /* NOTE: Further 17 registers set to 0. */
- },
- /*
- * NOTE: Following registers all set to 0:
- * - dmv_qpel_penalty,
- * - vp8_ctrl1,
- * - bit_cost_golden,
- * - loop_flt_delta.
- */
};
-const struct rk3288_vp8e_reg_params *rk3288_vpu_vp8e_get_dummy_params(void)
+const struct rockchip_reg_params *rk3288_vpu_vp8e_get_dummy_params(void)
{
return &dummy_encode_reg_params;
}
projects / firefly-linux-kernel-4.4.55.git / blobdiff