drm/rockchip: add rk3399 vop big csc support

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / rockchip / rockchip_vop_reg.c

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 8e27991a2ffb12c6a76d82ee7f536ebf47ff8b4a..533b9b24e25e26c067e4b21b9964a5d83a0412f7 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -53,6 +53,9 @@ static const uint32_t formats_win_full[] = {
        DRM_FORMAT_NV12,
        DRM_FORMAT_NV16,
        DRM_FORMAT_NV24,
+       DRM_FORMAT_NV12_10,
+       DRM_FORMAT_NV16_10,
+       DRM_FORMAT_NV24_10,
 };
 
 static const uint32_t formats_win_lite[] = {
@@ -104,6 +107,7 @@ static const struct vop_win_phy rk3288_win01_data = {
        .nformats = ARRAY_SIZE(formats_win_full),
        .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
        .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+       .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
        .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
        .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
        .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
@@ -170,6 +174,7 @@ static const struct vop_ctrl rk3288_ctrl_data = {
        .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
        .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
        .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
+       .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
        .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
        .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
        .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
@@ -180,7 +185,7 @@ static const struct vop_ctrl rk3288_ctrl_data = {
        .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
        .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
        .core_dclk_div = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 4, 3, 4, -1),
-       .p2i_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 5, 3, 4, -1),
+       .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
        .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
        .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
        .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
@@ -200,6 +205,14 @@ static const struct vop_ctrl rk3288_ctrl_data = {
        .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
        .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 
+       .afbdc_rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
+       .afbdc_en = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
+       .afbdc_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
+       .afbdc_format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
+       .afbdc_hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
+       .afbdc_hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
+       .afbdc_pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
+
        .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
        .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
 
@@ -371,17 +384,117 @@ static const struct vop_data rk3366_vop = {
        .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 };
 
+static const uint32_t vop_csc_y2r_bt601[] = {
+       0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
+       0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
+};
+
+static const uint32_t vop_csc_y2r_bt601_12_235[] = {
+       0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
+       0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
+};
+
+static const uint32_t vop_csc_r2y_bt601[] = {
+       0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
+       0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
+};
+
+static const uint32_t vop_csc_r2y_bt601_12_235[] = {
+       0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
+       0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
+};
+
+static const uint32_t vop_csc_y2r_bt709[] = {
+       0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
+       0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
+};
+
+static const uint32_t vop_csc_r2y_bt709[] = {
+       0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
+       0xffd7fe68, 0x00010200, 0x00080200, 0x00080200,
+};
+
+static const uint32_t vop_csc_y2r_bt2020[] = {
+       0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
+       0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
+};
+
+static const uint32_t vop_csc_r2y_bt2020[] = {
+       0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
+       0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
+};
+
+static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
+       0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
+       0x0000047a, 0x00000200, 0x00000200, 0x00000200,
+};
+
+static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
+       0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
+       0x00000394, 0x00000200, 0x00000200, 0x00000200,
+};
+
+static const struct vop_csc_table rk3399_csc_table = {
+       .y2r_bt601              = vop_csc_y2r_bt601,
+       .y2r_bt601_12_235       = vop_csc_y2r_bt601_12_235,
+       .r2y_bt601              = vop_csc_r2y_bt601,
+       .r2y_bt601_12_235       = vop_csc_r2y_bt601_12_235,
+
+       .y2r_bt709              = vop_csc_y2r_bt709,
+       .r2y_bt709              = vop_csc_r2y_bt709,
+
+       .y2r_bt2020             = vop_csc_y2r_bt2020,
+       .r2y_bt2020             = vop_csc_r2y_bt2020,
+
+       .r2r_bt709_to_bt2020    = vop_csc_r2r_bt709_to_bt2020,
+       .r2r_bt2020_to_bt709    = vop_csc_r2r_bt2020_to_bt709,
+};
+
+static const struct vop_csc rk3399_win0_csc = {
+       .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
+       .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
+       .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
+       .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
+       .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
+       .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
+};
+
+static const struct vop_csc rk3399_win1_csc = {
+       .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
+       .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
+       .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
+       .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
+       .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
+       .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
+};
+
+static const struct vop_win_data rk3399_vop_win_data[] = {
+       { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
+         .type = DRM_PLANE_TYPE_PRIMARY },
+       { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
+         .type = DRM_PLANE_TYPE_OVERLAY },
+       { .base = 0x00, .phy = &rk3368_win23_data,
+         .type = DRM_PLANE_TYPE_OVERLAY,
+         .area = rk3368_area_data,
+         .area_size = ARRAY_SIZE(rk3368_area_data), },
+       { .base = 0x50, .phy = &rk3368_win23_data,
+         .type = DRM_PLANE_TYPE_CURSOR,
+         .area = rk3368_area_data,
+         .area_size = ARRAY_SIZE(rk3368_area_data), },
+};
+
 static const struct vop_data rk3399_vop_big = {
        .version = VOP_VERSION(3, 5),
-       .feature = VOP_FEATURE_OUTPUT_10BIT,
+       .csc_table = &rk3399_csc_table,
+       .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
        .intr = &rk3366_vop_intr,
        .ctrl = &rk3288_ctrl_data,
-       .win = rk3368_vop_win_data,
-       .win_size = ARRAY_SIZE(rk3368_vop_win_data),
+       .win = rk3399_vop_win_data,
+       .win_size = ARRAY_SIZE(rk3399_vop_win_data),
 };
 
 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
-       { .base = 0x00, .phy = &rk3288_win01_data,
+       { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
          .type = DRM_PLANE_TYPE_PRIMARY },
        { .phy = NULL },
        { .base = 0x00, .phy = &rk3368_win23_data,
@@ -394,6 +507,7 @@ static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 
 static const struct vop_data rk3399_vop_lit = {
        .version = VOP_VERSION(3, 6),
+       .csc_table = &rk3399_csc_table,
        .intr = &rk3366_vop_intr,
        .ctrl = &rk3288_ctrl_data,
        .win = rk3399_vop_lit_win_data,
@@ -474,6 +588,7 @@ static const struct vop_intr rk3036_intr = {
 static const struct vop_ctrl rk3036_ctrl_data = {
        .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
        .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
+       .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
        .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
        .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
        .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),