#include <linux/reset.h>
#include <linux/delay.h>
+#include <linux/sort.h>
+#include <uapi/drm/rockchip_drm.h>
#include "rockchip_drm_drv.h"
#include "rockchip_drm_gem.h"
#include "rockchip_drm_fb.h"
#include "rockchip_drm_vop.h"
-#define __REG_SET_RELAXED(x, off, mask, shift, v) \
- vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
-#define __REG_SET_NORMAL(x, off, mask, shift, v) \
- vop_mask_write(x, off, (mask) << shift, (v) << shift)
+#define VOP_REG_SUPPORT(vop, reg) \
+ (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
+ reg.begin_minor <= VOP_MINOR(vop->data->version) && \
+ reg.end_minor >= VOP_MINOR(vop->data->version) && \
+ reg.mask))
-#define REG_SET(x, base, reg, v, mode) \
- __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
-#define REG_SET_MASK(x, base, reg, mask, v, mode) \
- __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v)
+#define VOP_WIN_SUPPORT(vop, win, name) \
+ VOP_REG_SUPPORT(vop, win->phy->name)
+
+#define VOP_CTRL_SUPPORT(vop, win, name) \
+ VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
+
+#define VOP_INTR_SUPPORT(vop, win, name) \
+ VOP_REG_SUPPORT(vop, vop->data->intr->name)
+
+#define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
+ vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
+
+#define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
+ do { \
+ if (VOP_REG_SUPPORT(vop, reg)) \
+ __REG_SET(vop, off + reg.offset, mask, reg.shift, \
+ v, reg.write_mask, relaxed); \
+ else \
+ dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
+ } while(0)
+
+#define REG_SET(x, name, off, reg, v, relaxed) \
+ _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
+#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
+ _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
#define VOP_WIN_SET(x, win, name, v) \
- REG_SET(x, win->base, win->phy->name, v, RELAXED)
+ REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
+#define VOP_WIN_SET_EXT(x, win, ext, name, v) \
+ REG_SET(x, name, win->offset, win->ext->name, v, true)
#define VOP_SCL_SET(x, win, name, v) \
- REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+ REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
#define VOP_SCL_SET_EXT(x, win, name, v) \
- REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
+ REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
+
#define VOP_CTRL_SET(x, name, v) \
- REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+ REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
#define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, &vop->data->ctrl->name)
#define VOP_INTR_SET(vop, name, mask, v) \
- REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
+ REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
+ mask, v, false)
+
#define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
#define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, &vop->data->intr->name, type)
+#define VOP_CTRL_GET(x, name) \
+ vop_read_reg(x, 0, &vop->data->ctrl->name)
+
#define VOP_WIN_GET(x, win, name) \
- vop_read_reg(x, win->base, &win->phy->name)
+ vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
+
+#define VOP_WIN_NAME(win, name) \
+ (vop_get_win_phy(win, &win->phy->name)->name)
#define VOP_WIN_GET_YRGBADDR(vop, win) \
- vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
+ vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
#define to_vop(x) container_of(x, struct vop, crtc)
#define to_vop_win(x) container_of(x, struct vop_win, base)
#define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
+struct vop_zpos {
+ int win_id;
+ int zpos;
+};
+
struct vop_plane_state {
struct drm_plane_state base;
int format;
+ int zpos;
struct drm_rect src;
struct drm_rect dest;
dma_addr_t yrgb_mst;
+ dma_addr_t uv_mst;
+ const uint32_t *y2r_table;
+ const uint32_t *r2r_table;
+ const uint32_t *r2y_table;
bool enable;
};
struct vop_win {
+ struct vop_win *parent;
struct drm_plane base;
- const struct vop_win_data *data;
+
+ int win_id;
+ int area_id;
+ uint32_t offset;
+ enum drm_plane_type type;
+ const struct vop_win_phy *phy;
+ const struct vop_csc *csc;
+ const uint32_t *data_formats;
+ uint32_t nformats;
struct vop *vop;
+ struct drm_property *rotation_prop;
struct vop_plane_state state;
};
struct drm_crtc crtc;
struct device *dev;
struct drm_device *drm_dev;
+ struct drm_property *plane_zpos_prop;
+ struct drm_property *plane_feature_prop;
+ bool is_iommu_enabled;
+ bool is_iommu_needed;
bool is_enabled;
/* mutex vsync_ work */
struct drm_pending_vblank_event *event;
const struct vop_data *data;
+ int num_wins;
uint32_t *regsbak;
void __iomem *regs;
}
static inline void vop_mask_write(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t v)
+ uint32_t mask, uint32_t shift, uint32_t v,
+ bool write_mask, bool relaxed)
{
- if (mask) {
+ if (!mask)
+ return;
+
+ if (write_mask) {
+ v = ((v & mask) << shift) | (mask << (shift + 16));
+ } else {
uint32_t cached_val = vop->regsbak[offset >> 2];
- cached_val = (cached_val & ~mask) | v;
- writel(cached_val, vop->regs + offset);
- vop->regsbak[offset >> 2] = cached_val;
+ v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
+ vop->regsbak[offset >> 2] = v;
}
+
+ if (relaxed)
+ writel_relaxed(v, vop->regs + offset);
+ else
+ writel(v, vop->regs + offset);
}
-static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t v)
+static inline const struct vop_win_phy *
+vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
{
- if (mask) {
- uint32_t cached_val = vop->regsbak[offset >> 2];
+ if (!reg->mask && win->parent)
+ return win->parent->phy;
- cached_val = (cached_val & ~mask) | v;
- writel_relaxed(cached_val, vop->regs + offset);
- vop->regsbak[offset >> 2] = cached_val;
- }
+ return win->phy;
}
static inline uint32_t vop_get_intr_type(struct vop *vop,
return ret;
}
+static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
+{
+ int i;
+
+ if (!table)
+ return;
+
+ for (i = 0; i < 8; i++)
+ vop_writel(vop, offset + i * 4, table[i]);
+}
+
static inline void vop_cfg_done(struct vop *vop)
{
VOP_CTRL_SET(vop, cfg_done, 1);
}
+static bool vop_is_allwin_disabled(struct vop *vop)
+{
+ int i;
+
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
+
+ if (VOP_WIN_GET(vop, win, enable) != 0)
+ return false;
+ }
+
+ return true;
+}
+
+static bool vop_is_cfg_done_complete(struct vop *vop)
+{
+ return VOP_CTRL_GET(vop, cfg_done) ? false : true;
+}
+
static bool has_rb_swapped(uint32_t format)
{
switch (format) {
return val;
}
-static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
- uint32_t src_w, uint32_t src_h, uint32_t dst_w,
- uint32_t dst_h, uint32_t pixel_format)
+static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
+ uint32_t src_w, uint32_t src_h, uint32_t dst_w,
+ uint32_t dst_h, uint32_t pixel_format)
{
uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
uint16_t cbcr_hor_scl_mode = SCALE_NONE;
uint16_t vsu_mode;
uint16_t lb_mode;
uint32_t val;
- int vskiplines;
+ int vskiplines = 0;
+
+ if (!win->phy->scl)
+ return;
if (dst_w > 3840) {
DRM_ERROR("Maximum destination width (3840) exceeded\n");
scl_cal_scale2(src_h, dst_h));
if (is_yuv) {
VOP_SCL_SET(vop, win, scale_cbcr_x,
- scl_cal_scale2(src_w, dst_w));
+ scl_cal_scale2(cbcr_src_w, dst_w));
VOP_SCL_SET(vop, win, scale_cbcr_y,
- scl_cal_scale2(src_h, dst_h));
+ scl_cal_scale2(cbcr_src_h, dst_h));
}
return;
}
VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
if (is_yuv) {
+ vskiplines = 0;
+
val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
dst_w, true, 0, NULL);
VOP_SCL_SET(vop, win, scale_cbcr_x, val);
}
}
+/*
+ * rk3399 colorspace path:
+ * Input Win csc Output
+ * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
+ * RGB --> R2Y __/
+ *
+ * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
+ * RGB --> 709To2020->R2Y __/
+ *
+ * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
+ * RGB --> R2Y __/
+ *
+ * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
+ * RGB --> 709To2020->R2Y __/
+ *
+ * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
+ * RGB --> R2Y __/
+ *
+ * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
+ * RGB --> R2Y(601) __/
+ *
+ * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
+ * RGB --> bypass __/
+ *
+ * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
+ *
+ * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
+ *
+ * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
+ *
+ * 11. RGB --> bypass --> RGB_OUTPUT(709)
+ */
+static int vop_csc_setup(const struct vop_csc_table *csc_table,
+ bool is_input_yuv, bool is_output_yuv,
+ int input_csc, int output_csc,
+ const uint32_t **y2r_table,
+ const uint32_t **r2r_table,
+ const uint32_t **r2y_table)
+{
+ *y2r_table = NULL;
+ *r2r_table = NULL;
+ *r2y_table = NULL;
+
+ if (is_output_yuv) {
+ if (output_csc == CSC_BT2020) {
+ if (is_input_yuv) {
+ if (input_csc == CSC_BT2020)
+ return 0;
+ *y2r_table = csc_table->y2r_bt709;
+ }
+ if (input_csc != CSC_BT2020)
+ *r2r_table = csc_table->r2r_bt709_to_bt2020;
+ *r2y_table = csc_table->r2y_bt2020;
+ } else {
+ if (is_input_yuv && input_csc == CSC_BT2020)
+ *y2r_table = csc_table->y2r_bt2020;
+ if (input_csc == CSC_BT2020)
+ *r2r_table = csc_table->r2r_bt2020_to_bt709;
+ if (!is_input_yuv || y2r_table) {
+ if (output_csc == CSC_BT709)
+ *r2y_table = csc_table->r2y_bt709;
+ else
+ *r2y_table = csc_table->r2y_bt601;
+ }
+ }
+
+ } else {
+ if (!is_input_yuv)
+ return 0;
+
+ /*
+ * is possible use bt2020 on rgb mode?
+ */
+ if (WARN_ON(output_csc == CSC_BT2020))
+ return -EINVAL;
+
+ if (input_csc == CSC_BT2020)
+ *y2r_table = csc_table->y2r_bt2020;
+ else if (input_csc == CSC_BT709)
+ *y2r_table = csc_table->y2r_bt709;
+ else
+ *y2r_table = csc_table->y2r_bt601;
+
+ if (input_csc == CSC_BT2020)
+ /*
+ * We don't have bt601 to bt709 table, force use bt709.
+ */
+ *r2r_table = csc_table->r2r_bt2020_to_bt709;
+ }
+
+ return 0;
+}
+
+static int vop_csc_atomic_check(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
+{
+ struct vop *vop = to_vop(crtc);
+ struct drm_atomic_state *state = crtc_state->state;
+ const struct vop_csc_table *csc_table = vop->data->csc_table;
+ struct drm_plane_state *pstate;
+ struct drm_plane *plane;
+ bool is_yuv;
+ int ret;
+
+ if (!csc_table)
+ return 0;
+
+ drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
+ struct vop_plane_state *vop_plane_state;
+
+ pstate = drm_atomic_get_plane_state(state, plane);
+ if (IS_ERR(pstate))
+ return PTR_ERR(pstate);
+ vop_plane_state = to_vop_plane_state(pstate);
+
+ if (!pstate->fb)
+ continue;
+ is_yuv = is_yuv_support(pstate->fb->pixel_format);
+
+ /*
+ * TODO: force set input and output csc mode.
+ */
+ ret = vop_csc_setup(csc_table, is_yuv, false,
+ CSC_BT709, CSC_BT709,
+ &vop_plane_state->y2r_table,
+ &vop_plane_state->r2r_table,
+ &vop_plane_state->r2y_table);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
{
unsigned long flags;
- if (WARN_ON(!vop->is_enabled))
- return;
-
spin_lock_irqsave(&vop->irq_lock, flags);
VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
{
unsigned long flags;
- if (WARN_ON(!vop->is_enabled))
- return;
-
spin_lock_irqsave(&vop->irq_lock, flags);
VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
static void vop_enable(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
- int ret;
-
- if (vop->is_enabled)
- return;
-
- ret = pm_runtime_get_sync(vop->dev);
- if (ret < 0) {
- dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
- return;
- }
+ int ret, i;
- ret = clk_enable(vop->hclk);
+ ret = clk_prepare_enable(vop->hclk);
if (ret < 0) {
dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
return;
}
- ret = clk_enable(vop->dclk);
+ ret = clk_prepare_enable(vop->dclk);
if (ret < 0) {
dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
goto err_disable_hclk;
}
- ret = clk_enable(vop->aclk);
+ ret = clk_prepare_enable(vop->aclk);
if (ret < 0) {
dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
goto err_disable_dclk;
}
- /*
- * Slave iommu shares power, irq and clock with vop. It was associated
- * automatically with this master device via common driver code.
- * Now that we have enabled the clock we attach it to the shared drm
- * mapping.
- */
- ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
- if (ret) {
- dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
- goto err_disable_aclk;
+ ret = pm_runtime_get_sync(vop->dev);
+ if (ret < 0) {
+ dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
+ return;
}
- memcpy(vop->regs, vop->regsbak, vop->len);
- /*
- * At here, vop clock & iommu is enable, R/W vop regs would be safe.
- */
+ memcpy(vop->regsbak, vop->regs, vop->len);
+
+ VOP_CTRL_SET(vop, global_regdone_en, 1);
+ VOP_CTRL_SET(vop, dsp_blank, 0);
+
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
+
+ VOP_WIN_SET(vop, win, gate, 1);
+ }
vop->is_enabled = true;
spin_lock(&vop->reg_lock);
return;
-err_disable_aclk:
- clk_disable(vop->aclk);
err_disable_dclk:
- clk_disable(vop->dclk);
+ clk_disable_unprepare(vop->dclk);
err_disable_hclk:
- clk_disable(vop->hclk);
+ clk_disable_unprepare(vop->hclk);
}
static void vop_crtc_disable(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
+ int i;
- if (!vop->is_enabled)
- return;
+ /*
+ * We need to make sure that all windows are disabled before we
+ * disable that crtc. Otherwise we might try to scan from a destroyed
+ * buffer later.
+ */
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
+
+ spin_lock(&vop->reg_lock);
+ VOP_WIN_SET(vop, win, enable, 0);
+ spin_unlock(&vop->reg_lock);
+ }
+ vop_cfg_done(vop);
drm_crtc_vblank_off(crtc);
disable_irq(vop->irq);
vop->is_enabled = false;
+ if (vop->is_iommu_enabled) {
+ /*
+ * vop standby complete, so iommu detach is safe.
+ */
+ rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
+ vop->is_iommu_enabled = false;
+ }
- /*
- * vop standby complete, so iommu detach is safe.
- */
- rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
-
- clk_disable(vop->dclk);
- clk_disable(vop->aclk);
- clk_disable(vop->hclk);
pm_runtime_put(vop->dev);
+ clk_disable_unprepare(vop->dclk);
+ clk_disable_unprepare(vop->aclk);
+ clk_disable_unprepare(vop->hclk);
}
static void vop_plane_destroy(struct drm_plane *plane)
drm_plane_cleanup(plane);
}
+static int vop_plane_prepare_fb(struct drm_plane *plane,
+ const struct drm_plane_state *new_state)
+{
+ if (plane->state->fb)
+ drm_framebuffer_reference(plane->state->fb);
+
+ return 0;
+}
+
+static void vop_plane_cleanup_fb(struct drm_plane *plane,
+ const struct drm_plane_state *old_state)
+{
+ if (old_state->fb)
+ drm_framebuffer_unreference(old_state->fb);
+}
+
static int vop_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
- struct vop_win *vop_win = to_vop_win(plane);
+ struct vop_win *win = to_vop_win(plane);
struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
- const struct vop_win_data *win = vop_win->data;
+ struct drm_crtc_state *crtc_state;
bool visible;
int ret;
struct drm_rect *dest = &vop_plane_state->dest;
DRM_PLANE_HELPER_NO_SCALING;
int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
DRM_PLANE_HELPER_NO_SCALING;
+ unsigned long offset;
+ dma_addr_t dma_addr;
crtc = crtc ? crtc : plane->state->crtc;
/*
*/
if (!crtc || !fb)
goto out_disable;
+
+ crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
src->x1 = state->src_x;
src->y1 = state->src_y;
src->x2 = state->src_x + state->src_w;
clip.x1 = 0;
clip.y1 = 0;
- clip.x2 = crtc->mode.hdisplay;
- clip.y2 = crtc->mode.vdisplay;
+ clip.x2 = crtc_state->mode.hdisplay;
+ clip.y2 = crtc_state->mode.vdisplay;
ret = drm_plane_helper_check_update(plane, crtc, state->fb,
src, dest, &clip,
if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
return -EINVAL;
+ offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
+ if (state->rotation & BIT(DRM_REFLECT_Y))
+ offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
+ else
+ offset += (src->y1 >> 16) * fb->pitches[0];
+
+ dma_addr = rockchip_fb_get_dma_addr(fb, 0);
+ vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
+ if (is_yuv_support(fb->pixel_format)) {
+ int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
+ int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
+ int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
+
+ offset = (src->x1 >> 16) * bpp / hsub;
+ offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
+
+ dma_addr = rockchip_fb_get_dma_addr(fb, 1);
+ dma_addr += offset + fb->offsets[1];
+ vop_plane_state->uv_mst = dma_addr;
+ }
+
vop_plane_state->enable = true;
return 0;
struct drm_plane_state *old_state)
{
struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
- struct vop_win *vop_win = to_vop_win(plane);
- const struct vop_win_data *win = vop_win->data;
+ struct vop_win *win = to_vop_win(plane);
struct vop *vop = to_vop(old_state->crtc);
if (!old_state->crtc)
{
struct drm_plane_state *state = plane->state;
struct drm_crtc *crtc = state->crtc;
- struct vop_win *vop_win = to_vop_win(plane);
+ struct vop_win *win = to_vop_win(plane);
struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
- const struct vop_win_data *win = vop_win->data;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
struct vop *vop = to_vop(state->crtc);
struct drm_framebuffer *fb = state->fb;
unsigned int actual_w, actual_h;
uint32_t act_info, dsp_info, dsp_st;
struct drm_rect *src = &vop_plane_state->src;
struct drm_rect *dest = &vop_plane_state->dest;
- struct drm_gem_object *obj, *uv_obj;
- struct rockchip_gem_object *rk_obj, *rk_uv_obj;
- unsigned long offset;
- dma_addr_t dma_addr;
+ const uint32_t *y2r_table = vop_plane_state->y2r_table;
+ const uint32_t *r2r_table = vop_plane_state->r2r_table;
+ const uint32_t *r2y_table = vop_plane_state->r2y_table;
+ int ymirror, xmirror;
uint32_t val;
bool rb_swap;
if (!crtc)
return;
- if (WARN_ON(!vop->is_enabled))
- return;
-
if (!vop_plane_state->enable) {
vop_plane_atomic_disable(plane, old_state);
return;
}
- obj = rockchip_fb_get_gem_obj(fb, 0);
- rk_obj = to_rockchip_obj(obj);
-
actual_w = drm_rect_width(src) >> 16;
actual_h = drm_rect_height(src) >> 16;
act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
- offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
- offset += (src->y1 >> 16) * fb->pitches[0];
- vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
+ ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
+ xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
spin_lock(&vop->reg_lock);
+ VOP_WIN_SET(vop, win, xmirror, xmirror);
+ VOP_WIN_SET(vop, win, ymirror, ymirror);
VOP_WIN_SET(vop, win, format, vop_plane_state->format);
VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
if (is_yuv_support(fb->pixel_format)) {
- int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
- int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
- int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
-
- uv_obj = rockchip_fb_get_gem_obj(fb, 1);
- rk_uv_obj = to_rockchip_obj(uv_obj);
-
- offset = (src->x1 >> 16) * bpp / hsub;
- offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
-
- dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
- VOP_WIN_SET(vop, win, uv_mst, dma_addr);
+ VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
}
- if (win->phy->scl)
- scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
- drm_rect_width(dest), drm_rect_height(dest),
- fb->pixel_format);
+ scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
+ drm_rect_width(dest), drm_rect_height(dest),
+ fb->pixel_format);
VOP_WIN_SET(vop, win, act_info, act_info);
VOP_WIN_SET(vop, win, dsp_info, dsp_info);
rb_swap = has_rb_swapped(fb->pixel_format);
VOP_WIN_SET(vop, win, rb_swap, rb_swap);
- if (is_alpha_support(fb->pixel_format)) {
+ if (is_alpha_support(fb->pixel_format) &&
+ (s->dsp_layer_sel & 0x3) != win->win_id) {
VOP_WIN_SET(vop, win, dst_alpha_ctl,
DST_FACTOR_M0(ALPHA_SRC_INVERSE));
val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
SRC_FACTOR_M0(ALPHA_ONE);
VOP_WIN_SET(vop, win, src_alpha_ctl, val);
+ VOP_WIN_SET(vop, win, alpha_mode, 1);
+ VOP_WIN_SET(vop, win, alpha_en, 1);
} else {
VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
+ VOP_WIN_SET(vop, win, alpha_en, 0);
}
+ if (win->csc) {
+ vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
+ vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
+ vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
+ VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
+ VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
+ VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
+ }
VOP_WIN_SET(vop, win, enable, 1);
spin_unlock(&vop->reg_lock);
+ vop->is_iommu_needed = true;
}
static const struct drm_plane_helper_funcs plane_helper_funcs = {
+ .prepare_fb = vop_plane_prepare_fb,
+ .cleanup_fb = vop_plane_cleanup_fb,
.atomic_check = vop_plane_atomic_check,
.atomic_update = vop_plane_atomic_update,
.atomic_disable = vop_plane_atomic_disable,
void vop_atomic_plane_reset(struct drm_plane *plane)
{
+ struct vop_win *win = to_vop_win(plane);
struct vop_plane_state *vop_plane_state =
to_vop_plane_state(plane->state);
if (!vop_plane_state)
return;
+ vop_plane_state->zpos = win->win_id;
plane->state = &vop_plane_state->base;
plane->state->plane = plane;
}
kfree(vop_state);
}
+static int vop_atomic_plane_set_property(struct drm_plane *plane,
+ struct drm_plane_state *state,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct vop_win *win = to_vop_win(plane);
+ struct vop_plane_state *plane_state = to_vop_plane_state(state);
+
+ if (property == win->vop->plane_zpos_prop) {
+ plane_state->zpos = val;
+ return 0;
+ }
+
+ if (property == win->rotation_prop) {
+ state->rotation = val;
+ return 0;
+ }
+
+ DRM_ERROR("failed to set vop plane property\n");
+ return -EINVAL;
+}
+
+static int vop_atomic_plane_get_property(struct drm_plane *plane,
+ const struct drm_plane_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct vop_win *win = to_vop_win(plane);
+ struct vop_plane_state *plane_state = to_vop_plane_state(state);
+
+ if (property == win->vop->plane_zpos_prop) {
+ *val = plane_state->zpos;
+ return 0;
+ }
+
+ if (property == win->rotation_prop) {
+ *val = state->rotation;
+ return 0;
+ }
+
+ DRM_ERROR("failed to get vop plane property\n");
+ return -EINVAL;
+}
+
static const struct drm_plane_funcs vop_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.reset = vop_atomic_plane_reset,
.atomic_duplicate_state = vop_atomic_plane_duplicate_state,
.atomic_destroy_state = vop_atomic_plane_destroy_state,
+ .atomic_set_property = vop_atomic_plane_set_property,
+ .atomic_get_property = vop_atomic_plane_get_property,
};
-int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
- int connector_type,
- int out_mode)
-{
- struct vop *vop = to_vop(crtc);
-
- if (WARN_ON(!vop->is_enabled))
- return -EINVAL;
-
- switch (connector_type) {
- case DRM_MODE_CONNECTOR_LVDS:
- VOP_CTRL_SET(vop, rgb_en, 1);
- break;
- case DRM_MODE_CONNECTOR_eDP:
- VOP_CTRL_SET(vop, edp_en, 1);
- break;
- case DRM_MODE_CONNECTOR_HDMIA:
- VOP_CTRL_SET(vop, hdmi_en, 1);
- break;
- case DRM_MODE_CONNECTOR_DSI:
- VOP_CTRL_SET(vop, mipi_en, 1);
- break;
- default:
- DRM_ERROR("unsupport connector_type[%d]\n", connector_type);
- return -EINVAL;
- };
- VOP_CTRL_SET(vop, out_mode, out_mode);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
-
static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
unsigned long flags;
- if (WARN_ON(!vop->is_enabled))
+ if (!vop->is_enabled)
return -EPERM;
spin_lock_irqsave(&vop->irq_lock, flags);
struct vop *vop = to_vop(crtc);
unsigned long flags;
- if (WARN_ON(!vop->is_enabled))
+ if (!vop->is_enabled)
return;
spin_lock_irqsave(&vop->irq_lock, flags);
{
struct vop *vop = to_vop(crtc);
- if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
- return false;
-
adjusted_mode->clock =
clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
static void vop_crtc_enable(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
- u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
- u16 hdisplay = adjusted_mode->hdisplay;
- u16 htotal = adjusted_mode->htotal;
- u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
+ u16 htotal = adjusted_mode->crtc_htotal;
+ u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
u16 hact_end = hact_st + hdisplay;
- u16 vdisplay = adjusted_mode->vdisplay;
- u16 vtotal = adjusted_mode->vtotal;
- u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
- u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
+ u16 vdisplay = adjusted_mode->crtc_vdisplay;
+ u16 vtotal = adjusted_mode->crtc_vtotal;
+ u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
+ u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
u16 vact_end = vact_st + vdisplay;
uint32_t val;
val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
VOP_CTRL_SET(vop, pin_pol, val);
+ switch (s->output_type) {
+ case DRM_MODE_CONNECTOR_LVDS:
+ VOP_CTRL_SET(vop, rgb_en, 1);
+ VOP_CTRL_SET(vop, rgb_pin_pol, val);
+ break;
+ case DRM_MODE_CONNECTOR_eDP:
+ VOP_CTRL_SET(vop, edp_en, 1);
+ VOP_CTRL_SET(vop, edp_pin_pol, val);
+ break;
+ case DRM_MODE_CONNECTOR_HDMIA:
+ VOP_CTRL_SET(vop, hdmi_en, 1);
+ VOP_CTRL_SET(vop, hdmi_pin_pol, val);
+ break;
+ case DRM_MODE_CONNECTOR_DSI:
+ VOP_CTRL_SET(vop, mipi_en, 1);
+ VOP_CTRL_SET(vop, mipi_pin_pol, val);
+ break;
+ default:
+ DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
+ }
+
+ if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
+ !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
+ s->output_mode = ROCKCHIP_OUT_MODE_P888;
+
+ VOP_CTRL_SET(vop, out_mode, s->output_mode);
VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
val = hact_st << 16;
VOP_CTRL_SET(vop, hact_st_end, val);
VOP_CTRL_SET(vop, hpost_st_end, val);
- VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
+ VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
val = vact_st << 16;
val |= vact_end;
VOP_CTRL_SET(vop, vact_st_end, val);
VOP_CTRL_SET(vop, vpost_st_end, val);
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ u16 vact_st_f1 = vtotal + vact_st + 1;
+ u16 vact_end_f1 = vact_st_f1 + vdisplay;
+
+ val = vact_st_f1 << 16 | vact_end_f1;
+ VOP_CTRL_SET(vop, vact_st_end_f1, val);
+ VOP_CTRL_SET(vop, vpost_st_end_f1, val);
+
+ val = vtotal << 16 | (vtotal + vsync_len);
+ VOP_CTRL_SET(vop, vs_st_end_f1, val);
+ VOP_CTRL_SET(vop, dsp_interlace, 1);
+ VOP_CTRL_SET(vop, p2i_en, 1);
+ } else {
+ VOP_CTRL_SET(vop, dsp_interlace, 0);
+ VOP_CTRL_SET(vop, p2i_en, 0);
+ }
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
VOP_CTRL_SET(vop, standby, 0);
}
-static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
- struct drm_crtc_state *old_crtc_state)
+static int vop_zpos_cmp(const void *a, const void *b)
+{
+ struct vop_zpos *pa = (struct vop_zpos *)a;
+ struct vop_zpos *pb = (struct vop_zpos *)b;
+
+ return pa->zpos - pb->zpos;
+}
+
+static int vop_crtc_atomic_check(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
{
+ struct drm_atomic_state *state = crtc_state->state;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+ struct drm_plane *plane;
+ struct drm_plane_state *pstate;
+ struct vop_plane_state *plane_state;
+ struct vop_zpos *pzpos;
+ int dsp_layer_sel = 0;
+ int i, j, cnt = 0, ret = 0;
+
+ ret = vop_csc_atomic_check(crtc, crtc_state);
+ if (ret)
+ return ret;
- if (WARN_ON(!vop->is_enabled))
- return;
+ pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
+ if (!pzpos)
+ return -ENOMEM;
+
+ for (i = 0; i < vop_data->win_size; i++) {
+ const struct vop_win_data *win_data = &vop_data->win[i];
+ struct vop_win *win;
+
+ if (!win_data->phy)
+ continue;
+
+ for (j = 0; j < vop->num_wins; j++) {
+ win = &vop->win[j];
+
+ if (win->win_id == i && !win->area_id)
+ break;
+ }
+ if (WARN_ON(j >= vop->num_wins)) {
+ ret = -EINVAL;
+ goto err_free_pzpos;
+ }
+
+ plane = &win->base;
+ pstate = state->plane_states[drm_plane_index(plane)];
+ /*
+ * plane might not have changed, in which case take
+ * current state:
+ */
+ if (!pstate)
+ pstate = plane->state;
+ plane_state = to_vop_plane_state(pstate);
+ pzpos[cnt].zpos = plane_state->zpos;
+ pzpos[cnt++].win_id = win->win_id;
+ }
+
+ sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
+
+ for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
+ const struct vop_win_data *win_data = &vop_data->win[i];
+ int shift = i * 2;
+
+ if (win_data->phy) {
+ struct vop_zpos *zpos = &pzpos[cnt++];
+
+ dsp_layer_sel |= zpos->win_id << shift;
+ } else {
+ dsp_layer_sel |= i << shift;
+ }
+ }
+
+ s->dsp_layer_sel = dsp_layer_sel;
+
+err_free_pzpos:
+ kfree(pzpos);
+ return ret;
+}
+
+static void vop_cfg_update(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct rockchip_crtc_state *s =
+ to_rockchip_crtc_state(crtc->state);
+ struct vop *vop = to_vop(crtc);
spin_lock(&vop->reg_lock);
+ VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
vop_cfg_done(vop);
spin_unlock(&vop->reg_lock);
}
+static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct vop *vop = to_vop(crtc);
+
+ if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
+ int ret;
+ if (!vop_is_allwin_disabled(vop)) {
+ vop_cfg_update(crtc, old_crtc_state);
+ while(!vop_is_cfg_done_complete(vop));
+ }
+ ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
+ if (ret) {
+ dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
+ }
+ vop->is_iommu_enabled = true;
+ }
+
+ vop_cfg_update(crtc, old_crtc_state);
+}
+
static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
.enable = vop_crtc_enable,
.disable = vop_crtc_disable,
.mode_fixup = vop_crtc_mode_fixup,
+ .atomic_check = vop_crtc_atomic_check,
.atomic_flush = vop_crtc_atomic_flush,
.atomic_begin = vop_crtc_atomic_begin,
};
drm_crtc_cleanup(crtc);
}
-static const struct drm_crtc_funcs vop_crtc_funcs = {
- .set_config = drm_atomic_helper_set_config,
- .page_flip = drm_atomic_helper_page_flip,
- .destroy = vop_crtc_destroy,
- .reset = drm_atomic_helper_crtc_reset,
- .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
-};
+static void vop_crtc_reset(struct drm_crtc *crtc)
+{
+ if (crtc->state)
+ __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
+ kfree(crtc->state);
+
+ crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
+ if (crtc->state)
+ crtc->state->crtc = crtc;
+}
-static bool vop_win_pending_is_complete(struct vop_win *vop_win)
+static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
{
- struct drm_plane *plane = &vop_win->base;
- struct vop_plane_state *state = to_vop_plane_state(plane->state);
- dma_addr_t yrgb_mst;
+ struct rockchip_crtc_state *rockchip_state;
- if (!state->enable)
- return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
+ rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
+ if (!rockchip_state)
+ return NULL;
- yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
+ __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
+ return &rockchip_state->base;
+}
- return yrgb_mst == state->yrgb_mst;
+static void vop_crtc_destroy_state(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
+{
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
+
+ __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
+ kfree(s);
}
+static const struct drm_crtc_funcs vop_crtc_funcs = {
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .destroy = vop_crtc_destroy,
+ .reset = vop_crtc_reset,
+ .atomic_duplicate_state = vop_crtc_duplicate_state,
+ .atomic_destroy_state = vop_crtc_destroy_state,
+};
+
static void vop_handle_vblank(struct vop *vop)
{
struct drm_device *drm = vop->drm_dev;
struct drm_crtc *crtc = &vop->crtc;
unsigned long flags;
- int i;
- for (i = 0; i < vop->data->win_size; i++) {
- if (!vop_win_pending_is_complete(&vop->win[i]))
- return;
- }
+ if (!vop_is_cfg_done_complete(vop))
+ return;
if (vop->event) {
spin_lock_irqsave(&drm->event_lock, flags);
return ret;
}
+static int vop_plane_init(struct vop *vop, struct vop_win *win,
+ unsigned long possible_crtcs)
+{
+ struct drm_plane *share = NULL;
+ unsigned int rotations = 0;
+ struct drm_property *prop;
+ uint64_t feature = 0;
+ int ret;
+
+ if (win->parent)
+ share = &win->parent->base;
+
+ ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
+ possible_crtcs, &vop_plane_funcs,
+ win->data_formats, win->nformats, win->type);
+ if (ret) {
+ DRM_ERROR("failed to initialize plane\n");
+ return ret;
+ }
+ drm_plane_helper_add(&win->base, &plane_helper_funcs);
+ drm_object_attach_property(&win->base.base,
+ vop->plane_zpos_prop, win->win_id);
+
+ if (VOP_WIN_SUPPORT(vop, win, xmirror))
+ rotations |= BIT(DRM_REFLECT_X);
+
+ if (VOP_WIN_SUPPORT(vop, win, ymirror))
+ rotations |= BIT(DRM_REFLECT_Y);
+
+ if (rotations) {
+ rotations |= BIT(DRM_ROTATE_0);
+ prop = drm_mode_create_rotation_property(vop->drm_dev,
+ rotations);
+ if (!prop) {
+ DRM_ERROR("failed to create zpos property\n");
+ return -EINVAL;
+ }
+ drm_object_attach_property(&win->base.base, prop,
+ BIT(DRM_ROTATE_0));
+ win->rotation_prop = prop;
+ }
+ if (win->phy->scl)
+ feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
+ if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
+ VOP_WIN_SUPPORT(vop, win, alpha_en))
+ feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
+
+ drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
+ feature);
+
+ return 0;
+}
+
static int vop_create_crtc(struct vop *vop)
{
- const struct vop_data *vop_data = vop->data;
struct device *dev = vop->dev;
struct drm_device *drm_dev = vop->drm_dev;
- struct drm_plane *primary = NULL, *cursor = NULL, *plane;
+ struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
struct drm_crtc *crtc = &vop->crtc;
struct device_node *port;
int ret;
* to pass them to drm_crtc_init_with_planes, which sets the
* "possible_crtcs" to the newly initialized crtc.
*/
- for (i = 0; i < vop_data->win_size; i++) {
- struct vop_win *vop_win = &vop->win[i];
- const struct vop_win_data *win_data = vop_win->data;
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
- if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
- win_data->type != DRM_PLANE_TYPE_CURSOR)
+ if (win->type != DRM_PLANE_TYPE_PRIMARY &&
+ win->type != DRM_PLANE_TYPE_CURSOR)
continue;
- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
- 0, &vop_plane_funcs,
- win_data->phy->data_formats,
- win_data->phy->nformats,
- win_data->type, NULL);
- if (ret) {
- DRM_ERROR("failed to initialize plane\n");
+ ret = vop_plane_init(vop, win, 0);
+ if (ret)
goto err_cleanup_planes;
- }
- plane = &vop_win->base;
- drm_plane_helper_add(plane, &plane_helper_funcs);
+ plane = &win->base;
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
primary = plane;
else if (plane->type == DRM_PLANE_TYPE_CURSOR)
cursor = plane;
+
}
ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
&vop_crtc_funcs, NULL);
if (ret)
- return ret;
+ goto err_cleanup_planes;
drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
* Create drm_planes for overlay windows with possible_crtcs restricted
* to the newly created crtc.
*/
- for (i = 0; i < vop_data->win_size; i++) {
- struct vop_win *vop_win = &vop->win[i];
- const struct vop_win_data *win_data = vop_win->data;
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
- if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
+ if (win->type != DRM_PLANE_TYPE_OVERLAY)
continue;
- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
- possible_crtcs,
- &vop_plane_funcs,
- win_data->phy->data_formats,
- win_data->phy->nformats,
- win_data->type, NULL);
- if (ret) {
- DRM_ERROR("failed to initialize overlay plane\n");
+ ret = vop_plane_init(vop, win, possible_crtcs);
+ if (ret)
goto err_cleanup_crtc;
- }
- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
}
port = of_get_child_by_name(dev->of_node, "port");
if (!port) {
DRM_ERROR("no port node found in %s\n",
dev->of_node->full_name);
+ ret = -ENOENT;
goto err_cleanup_crtc;
}
err_cleanup_crtc:
drm_crtc_cleanup(crtc);
err_cleanup_planes:
- list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
+ list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
+ head)
drm_plane_cleanup(plane);
return ret;
}
static void vop_destroy_crtc(struct vop *vop)
{
struct drm_crtc *crtc = &vop->crtc;
+ struct drm_device *drm_dev = vop->drm_dev;
+ struct drm_plane *plane, *tmp;
rockchip_unregister_crtc_funcs(crtc);
of_node_put(crtc->port);
- drm_crtc_cleanup(crtc);
-}
-
-static int vop_initial(struct vop *vop)
-{
- const struct vop_data *vop_data = vop->data;
- const struct vop_reg_data *init_table = vop_data->init_table;
- struct reset_control *ahb_rst;
- int i, ret;
-
- vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
- if (IS_ERR(vop->hclk)) {
- dev_err(vop->dev, "failed to get hclk source\n");
- return PTR_ERR(vop->hclk);
- }
- vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
- if (IS_ERR(vop->aclk)) {
- dev_err(vop->dev, "failed to get aclk source\n");
- return PTR_ERR(vop->aclk);
- }
- vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
- if (IS_ERR(vop->dclk)) {
- dev_err(vop->dev, "failed to get dclk source\n");
- return PTR_ERR(vop->dclk);
- }
-
- ret = clk_prepare(vop->dclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to prepare dclk\n");
- return ret;
- }
-
- /* Enable both the hclk and aclk to setup the vop */
- ret = clk_prepare_enable(vop->hclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to prepare/enable hclk\n");
- goto err_unprepare_dclk;
- }
-
- ret = clk_prepare_enable(vop->aclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to prepare/enable aclk\n");
- goto err_disable_hclk;
- }
/*
- * do hclk_reset, reset all vop registers.
+ * We need to cleanup the planes now. Why?
+ *
+ * The planes are "&vop->win[i].base". That means the memory is
+ * all part of the big "struct vop" chunk of memory. That memory
+ * was devm allocated and associated with this component. We need to
+ * free it ourselves before vop_unbind() finishes.
*/
- ahb_rst = devm_reset_control_get(vop->dev, "ahb");
- if (IS_ERR(ahb_rst)) {
- dev_err(vop->dev, "failed to get ahb reset\n");
- ret = PTR_ERR(ahb_rst);
- goto err_disable_aclk;
- }
- reset_control_assert(ahb_rst);
- usleep_range(10, 20);
- reset_control_deassert(ahb_rst);
-
- memcpy(vop->regsbak, vop->regs, vop->len);
-
- for (i = 0; i < vop_data->table_size; i++)
- vop_writel(vop, init_table[i].offset, init_table[i].value);
-
- for (i = 0; i < vop_data->win_size; i++) {
- const struct vop_win_data *win = &vop_data->win[i];
-
- VOP_WIN_SET(vop, win, enable, 0);
- }
-
- vop_cfg_done(vop);
+ list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
+ head)
+ vop_plane_destroy(plane);
/*
- * do dclk_reset, let all config take affect.
+ * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
+ * references the CRTC.
*/
- vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
- if (IS_ERR(vop->dclk_rst)) {
- dev_err(vop->dev, "failed to get dclk reset\n");
- ret = PTR_ERR(vop->dclk_rst);
- goto err_disable_aclk;
- }
- reset_control_assert(vop->dclk_rst);
- usleep_range(10, 20);
- reset_control_deassert(vop->dclk_rst);
-
- clk_disable(vop->hclk);
- clk_disable(vop->aclk);
-
- vop->is_enabled = false;
-
- return 0;
-
-err_disable_aclk:
- clk_disable_unprepare(vop->aclk);
-err_disable_hclk:
- clk_disable_unprepare(vop->hclk);
-err_unprepare_dclk:
- clk_unprepare(vop->dclk);
- return ret;
+ drm_crtc_cleanup(crtc);
}
/*
* Initialize the vop->win array elements.
*/
-static void vop_win_init(struct vop *vop)
+static int vop_win_init(struct vop *vop)
{
const struct vop_data *vop_data = vop->data;
- unsigned int i;
+ unsigned int i, j;
+ unsigned int num_wins = 0;
+ struct drm_property *prop;
+ static const struct drm_prop_enum_list props[] = {
+ { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
+ { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
+ };
for (i = 0; i < vop_data->win_size; i++) {
- struct vop_win *vop_win = &vop->win[i];
+ struct vop_win *vop_win = &vop->win[num_wins];
const struct vop_win_data *win_data = &vop_data->win[i];
- vop_win->data = win_data;
+ if (!win_data->phy)
+ continue;
+
+ vop_win->phy = win_data->phy;
+ vop_win->csc = win_data->csc;
+ vop_win->offset = win_data->base;
+ vop_win->type = win_data->type;
+ vop_win->data_formats = win_data->phy->data_formats;
+ vop_win->nformats = win_data->phy->nformats;
vop_win->vop = vop;
+ vop_win->win_id = i;
+ vop_win->area_id = 0;
+ num_wins++;
+
+ for (j = 0; j < win_data->area_size; j++) {
+ struct vop_win *vop_area = &vop->win[num_wins];
+ const struct vop_win_phy *area = win_data->area[j];
+
+ vop_area->parent = vop_win;
+ vop_area->offset = vop_win->offset;
+ vop_area->phy = area;
+ vop_area->type = DRM_PLANE_TYPE_OVERLAY;
+ vop_area->data_formats = vop_win->data_formats;
+ vop_area->nformats = vop_win->nformats;
+ vop_area->vop = vop;
+ vop_area->win_id = i;
+ vop_area->area_id = j;
+ num_wins++;
+ }
+ }
+
+ vop->num_wins = num_wins;
+
+ prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
+ "ZPOS", 0, vop->data->win_size);
+ if (!prop) {
+ DRM_ERROR("failed to create zpos property\n");
+ return -EINVAL;
}
+ vop->plane_zpos_prop = prop;
+
+ vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
+ DRM_MODE_PROP_IMMUTABLE, "FEATURE",
+ props, ARRAY_SIZE(props),
+ BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
+ BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
+ if (!vop->plane_feature_prop) {
+ DRM_ERROR("failed to create feature property\n");
+ return -EINVAL;
+ }
+
+ return 0;
}
static int vop_bind(struct device *dev, struct device *master, void *data)
struct vop *vop;
struct resource *res;
size_t alloc_size;
- int ret, irq;
+ int ret, irq, i;
+ int num_wins = 0;
vop_data = of_device_get_match_data(dev);
if (!vop_data)
return -ENODEV;
+ for (i = 0; i < vop_data->win_size; i++) {
+ const struct vop_win_data *win_data = &vop_data->win[i];
+
+ num_wins += win_data->area_size + 1;
+ }
+
/* Allocate vop struct and its vop_win array */
- alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
+ alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
if (!vop)
return -ENOMEM;
vop->dev = dev;
vop->data = vop_data;
vop->drm_dev = drm_dev;
+ vop->num_wins = num_wins;
dev_set_drvdata(dev, vop);
- vop_win_init(vop);
+ ret = vop_win_init(vop);
+ if (ret)
+ return ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
vop->len = resource_size(res);
if (!vop->regsbak)
return -ENOMEM;
- ret = vop_initial(vop);
- if (ret < 0) {
- dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
- return ret;
+ vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
+ if (IS_ERR(vop->hclk)) {
+ dev_err(vop->dev, "failed to get hclk source\n");
+ return PTR_ERR(vop->hclk);
+ }
+ vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
+ if (IS_ERR(vop->aclk)) {
+ dev_err(vop->dev, "failed to get aclk source\n");
+ return PTR_ERR(vop->aclk);
+ }
+ vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
+ if (IS_ERR(vop->dclk)) {
+ dev_err(vop->dev, "failed to get dclk source\n");
+ return PTR_ERR(vop->dclk);
}
irq = platform_get_irq(pdev, 0);
projects / firefly-linux-kernel-4.4.55.git / blobdiff