revert android-tegra-2.6.36-honeycomb-mr1-9001adc to v2.6.36

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / r600.c

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 74b9fb7a71df3214d1724955afc578c8bad8e582..7b65e4efe8af61e2df5404ea52c468fe8ee564db 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -97,8 +97,14 @@ u32 rv6xx_get_temp(struct radeon_device *rdev)
 {
        u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
                ASIC_T_SHIFT;
+       u32 actual_temp = 0;
 
-       return temp * 1000;
+       if ((temp >> 7) & 1)
+               actual_temp = 0;
+       else
+               actual_temp = (temp >> 1) & 0xff;
+
+       return actual_temp * 1000;
 }
 
 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
@@ -878,15 +884,12 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
        u32 tmp;
 
        /* flush hdp cache so updates hit vram */
-       if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
-           !(rdev->flags & RADEON_IS_AGP)) {
+       if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
                void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
                u32 tmp;
 
                /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
                 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
-                * This seems to cause problems on some AGP cards. Just use the old
-                * method for them.
                 */
                WREG32(HDP_DEBUG1, 0);
                tmp = readl((void __iomem *)ptr);
@@ -1198,10 +1201,8 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
                                mc->vram_end, mc->real_vram_size >> 20);
        } else {
                u64 base = 0;
-               if (rdev->flags & RADEON_IS_IGP) {
-                       base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
-                       base <<= 24;
-               }
+               if (rdev->flags & RADEON_IS_IGP)
+                       base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
                radeon_vram_location(rdev, &rdev->mc, base);
                rdev->mc.gtt_base_align = 0;
                radeon_gtt_location(rdev, mc);
@@ -1607,11 +1608,8 @@ void r600_gpu_init(struct radeon_device *rdev)
        rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
        rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
        tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
-       tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
-       if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
-               rdev->config.r600.tiling_group_size = 512;
-       else
-               rdev->config.r600.tiling_group_size = 256;
+       tiling_config |= GROUP_SIZE(0);
+       rdev->config.r600.tiling_group_size = 256;
        tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
        if (tmp > 3) {
                tiling_config |= ROW_TILING(3);
@@ -3530,12 +3528,10 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
 {
        /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
-        * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
-        * This seems to cause problems on some AGP cards. Just use the old
-        * method for them.
+        * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
         */
        if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
-           rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
+           rdev->vram_scratch.ptr) {
                void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
                u32 tmp;