drm/radeon/kms/pm: add asic specific callbacks for setting power state (v2)

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / r100.c

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 7a4a4fc276b3d2bad49827abc48f687c4de5c541..b076b96f8b6c23b6c5cd7d60a9b576a8f2794128 100644 (file)
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -26,6 +26,7 @@
  *          Jerome Glisse
  */
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "drm.h"
 #include "radeon_drm.h"
@@ -66,6 +67,51 @@ MODULE_FIRMWARE(FIRMWARE_R520);
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  */
 
+void r100_set_power_state(struct radeon_device *rdev)
+{
+       /* if *_clock_mode are the same, *_power_state are as well */
+       if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode)
+               return;
+
+       DRM_INFO("Setting: e: %d m: %d p: %d\n",
+                rdev->pm.requested_clock_mode->sclk,
+                rdev->pm.requested_clock_mode->mclk,
+                rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
+
+       /* set pcie lanes */
+       /* TODO */
+
+       /* set voltage */
+       /* TODO */
+
+       /* set engine clock */
+       radeon_sync_with_vblank(rdev);
+       radeon_pm_debug_check_in_vbl(rdev, false);
+       radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk);
+       radeon_pm_debug_check_in_vbl(rdev, true);
+
+#if 0
+       /* set memory clock */
+       if (rdev->asic->set_memory_clock) {
+               radeon_sync_with_vblank(rdev);
+               radeon_pm_debug_check_in_vbl(rdev, false);
+               radeon_set_memory_clock(rdev, rdev->pm.requested_clock_mode->mclk);
+               radeon_pm_debug_check_in_vbl(rdev, true);
+       }
+#endif
+
+       rdev->pm.current_power_state = rdev->pm.requested_power_state;
+       rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode;
+}
+
+bool r100_gui_idle(struct radeon_device *rdev)
+{
+       if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
+               return false;
+       else
+               return true;
+}
+
 /* hpd for digital panel detect/disconnect */
 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 {
@@ -253,6 +299,9 @@ int r100_irq_set(struct radeon_device *rdev)
        if (rdev->irq.sw_int) {
                tmp |= RADEON_SW_INT_ENABLE;
        }
+       if (rdev->irq.gui_idle) {
+               tmp |= RADEON_GUI_IDLE_MASK;
+       }
        if (rdev->irq.crtc_vblank_int[0]) {
                tmp |= RADEON_CRTC_VBLANK_MASK;
        }
@@ -287,6 +336,12 @@ static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
                RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
                RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 
+       /* the interrupt works, but the status bit is permanently asserted */
+       if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
+               if (!rdev->irq.gui_idle_acked)
+                       irq_mask |= RADEON_GUI_IDLE_STAT;
+       }
+
        if (irqs) {
                WREG32(RADEON_GEN_INT_STATUS, irqs);
        }
@@ -298,6 +353,9 @@ int r100_irq_process(struct radeon_device *rdev)
        uint32_t status, msi_rearm;
        bool queue_hotplug = false;
 
+       /* reset gui idle ack.  the status bit is broken */
+       rdev->irq.gui_idle_acked = false;
+
        status = r100_irq_ack(rdev);
        if (!status) {
                return IRQ_NONE;
@@ -310,6 +368,12 @@ int r100_irq_process(struct radeon_device *rdev)
                if (status & RADEON_SW_INT_TEST) {
                        radeon_fence_process(rdev);
                }
+               /* gui idle interrupt */
+               if (status & RADEON_GUI_IDLE_STAT) {
+                       rdev->irq.gui_idle_acked = true;
+                       rdev->pm.gui_idle = true;
+                       wake_up(&rdev->irq.idle_queue);
+               }
                /* Vertical blank interrupts */
                if (status & RADEON_CRTC_VBLANK_STAT) {
                        drm_handle_vblank(rdev->ddev, 0);
@@ -331,6 +395,8 @@ int r100_irq_process(struct radeon_device *rdev)
                }
                status = r100_irq_ack(rdev);
        }
+       /* reset gui idle ack.  the status bit is broken */
+       rdev->irq.gui_idle_acked = false;
        if (queue_hotplug)
                queue_work(rdev->wq, &rdev->hotplug_work);
        if (rdev->msi_enabled) {
@@ -2035,11 +2101,6 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
                else
                        rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
        }
-       /* FIXME remove this once we support unmappable VRAM */
-       if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
-               rdev->mc.mc_vram_size = rdev->mc.aper_size;
-               rdev->mc.real_vram_size = rdev->mc.aper_size;
-       }
 }
 
 void r100_vga_set_state(struct radeon_device *rdev, bool state)
@@ -2924,7 +2985,7 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
 {
        struct radeon_bo *robj;
        unsigned long size;
-       unsigned u, i, w, h;
+       unsigned u, i, w, h, d;
        int ret;
 
        for (u = 0; u < track->num_texture; u++) {
@@ -2956,20 +3017,25 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
                        h = h / (1 << i);
                        if (track->textures[u].roundup_h)
                                h = roundup_pow_of_two(h);
+                       if (track->textures[u].tex_coord_type == 1) {
+                               d = (1 << track->textures[u].txdepth) / (1 << i);
+                               if (!d)
+                                       d = 1;
+                       } else {
+                               d = 1;
+                       }
                        if (track->textures[u].compress_format) {
 
-                               size += r100_track_compress_size(track->textures[u].compress_format, w, h);
+                               size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
                                /* compressed textures are block based */
                        } else
-                               size += w * h;
+                               size += w * h * d;
                }
                size *= track->textures[u].cpp;
 
                switch (track->textures[u].tex_coord_type) {
                case 0:
-                       break;
                case 1:
-                       size *= (1 << track->textures[u].txdepth);
                        break;
                case 2:
                        if (track->separate_cube) {
@@ -3040,7 +3106,11 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
                }
        }
        prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
-       nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
+       if (track->vap_vf_cntl & (1 << 14)) {
+               nverts = track->vap_alt_nverts;
+       } else {
+               nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
+       }
        switch (prim_walk) {
        case 1:
                for (i = 0; i < track->num_arrays; i++) {