Merge branches 'pm-domains' and 'pm-cpufreq'

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / evergreen_cs.c

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4453799fb6769ddbe5ccf9ddedd1fc5bd6d16c8b..46f87d4aaf31fef4ae90d50321aee3f67439031f 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -447,7 +447,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
                 * command stream.
                 */
                if (!surf.mode) {
-                       volatile u32 *ib = p->ib.ptr;
+                       uint32_t *ib = p->ib.ptr;
                        unsigned long tmp, nby, bsize, size, min = 0;
 
                        /* find the height the ddx wants */
@@ -1773,7 +1773,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
 {
        struct radeon_bo_list *reloc;
        struct evergreen_cs_track *track;
-       volatile u32 *ib;
+       uint32_t *ib;
        unsigned idx;
        unsigned i;
        unsigned start_reg, end_reg, reg;
@@ -2299,11 +2299,10 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
                        return -EINVAL;
                }
-               for (i = 0; i < pkt->count; i++) {
-                       reg = start_reg + (4 * i);
+               for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
                        if (evergreen_is_safe_reg(p, reg))
                                continue;
-                       r = evergreen_cs_handle_reg(p, reg, idx + 1 + i);
+                       r = evergreen_cs_handle_reg(p, reg, idx);
                        if (r)
                                return r;
                }
@@ -2317,11 +2316,10 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
                        return -EINVAL;
                }
-               for (i = 0; i < pkt->count; i++) {
-                       reg = start_reg + (4 * i);
+               for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
                        if (evergreen_is_safe_reg(p, reg))
                                continue;
-                       r = evergreen_cs_handle_reg(p, reg, idx + 1 + i);
+                       r = evergreen_cs_handle_reg(p, reg, idx);
                        if (r)
                                return r;
                }
@@ -2749,7 +2747,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
        struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
        struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;
        u32 header, cmd, count, sub_cmd;
-       volatile u32 *ib = p->ib.ptr;
+       uint32_t *ib = p->ib.ptr;
        u32 idx;
        u64 src_offset, dst_offset, dst2_offset;
        int r;