}
}
-static uint32_t
-nouveau_mem_detect_nv04(struct drm_device *dev)
-{
- uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
-
- if (boot0 & 0x00000100)
- return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
-
- switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
- case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
- return 32 * 1024 * 1024;
- case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
- return 16 * 1024 * 1024;
- case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
- return 8 * 1024 * 1024;
- case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
- return 4 * 1024 * 1024;
- }
-
- return 0;
-}
-
-static uint32_t
-nouveau_mem_detect_nforce(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct pci_dev *bridge;
- uint32_t mem;
-
- bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
- if (!bridge) {
- NV_ERROR(dev, "no bridge device\n");
- return 0;
- }
-
- if (dev_priv->flags & NV_NFORCE) {
- pci_read_config_dword(bridge, 0x7C, &mem);
- return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
- } else
- if (dev_priv->flags & NV_NFORCE2) {
- pci_read_config_dword(bridge, 0x84, &mem);
- return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
- }
-
- NV_ERROR(dev, "impossible!\n");
- return 0;
-}
-
-int
-nouveau_mem_detect(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- if (dev_priv->card_type == NV_04) {
- dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
- } else
- if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
- dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
- } else
- if (dev_priv->card_type < NV_50) {
- dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
- dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
- }
-
- if (dev_priv->vram_size)
- return 0;
- return -ENOMEM;
-}
-
bool
nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
{
return 0;
}
+static const struct vram_types {
+ int value;
+ const char *name;
+} vram_type_map[] = {
+ { NV_MEM_TYPE_STOLEN , "stolen system memory" },
+ { NV_MEM_TYPE_SGRAM , "SGRAM" },
+ { NV_MEM_TYPE_SDRAM , "SDRAM" },
+ { NV_MEM_TYPE_DDR1 , "DDR1" },
+ { NV_MEM_TYPE_DDR2 , "DDR2" },
+ { NV_MEM_TYPE_DDR3 , "DDR3" },
+ { NV_MEM_TYPE_GDDR2 , "GDDR2" },
+ { NV_MEM_TYPE_GDDR3 , "GDDR3" },
+ { NV_MEM_TYPE_GDDR4 , "GDDR4" },
+ { NV_MEM_TYPE_GDDR5 , "GDDR5" },
+ { NV_MEM_TYPE_UNKNOWN, "unknown type" }
+};
+
int
nouveau_mem_vram_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
+ const struct vram_types *vram_type;
int ret, dma_bits;
dma_bits = 32;
return ret;
}
- NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
+ vram_type = vram_type_map;
+ while (vram_type->value != NV_MEM_TYPE_UNKNOWN) {
+ if (nouveau_vram_type) {
+ if (!strcasecmp(nouveau_vram_type, vram_type->name))
+ break;
+ dev_priv->vram_type = vram_type->value;
+ } else {
+ if (vram_type->value == dev_priv->vram_type)
+ break;
+ }
+ vram_type++;
+ }
+
+ NV_INFO(dev, "Detected %dMiB VRAM (%s)\n",
+ (int)(dev_priv->vram_size >> 20), vram_type->name);
if (dev_priv->vram_sys_base) {
NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
dev_priv->vram_sys_base);
/* XXX: For now a dummy. More samples required, possibly even a card
* Called from nouveau_perf.c */
-void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
- struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
- struct nouveau_pm_memtiming *timing) {
+void nv30_mem_timing_entry(struct drm_device *dev,
+ struct nouveau_pm_tbl_header *hdr,
+ struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
+ struct nouveau_pm_memtiming *timing)
+{
- NV_DEBUG(dev,"Timing entry format unknown, please contact nouveau developers");
+ NV_DEBUG(dev, "Timing entry format unknown, "
+ "please contact nouveau developers");
}
-void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
- struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
- struct nouveau_pm_memtiming *timing) {
+void nv40_mem_timing_entry(struct drm_device *dev,
+ struct nouveau_pm_tbl_header *hdr,
+ struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
+ struct nouveau_pm_memtiming *timing)
+{
timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP);
1 << 16 |
(e->tUNK_1 + 2 + magic_number) << 8 |
(e->tCL + 2 - magic_number);
- timing->reg_2 = (magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10);
+ timing->reg_2 = magic_number << 24 | e->tUNK_12 << 16 |
+ e->tUNK_11 << 8 | e->tUNK_10;
timing->reg_2 |= 0x20200000;
NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id,
- timing->reg_0, timing->reg_1,timing->reg_2);
+ timing->reg_0, timing->reg_1, timing->reg_2);
}
-void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr,
- struct nouveau_pm_tbl_entry *e, uint8_t magic_number,struct nouveau_pm_memtiming *timing) {
+void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P,
+ struct nouveau_pm_tbl_header *hdr,
+ struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
+ struct nouveau_pm_memtiming *timing)
+{
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint8_t unk18 = 1,
timing->reg_1 = (e->tWR + unk19 + 1 + magic_number) << 24 |
max(unk18, (u8) 1) << 16 |
(e->tUNK_1 + unk19 + 1 + magic_number) << 8;
- if (dev_priv->chipset == 0xa8) {
+ if (dev_priv->chipset == 0xa8)
timing->reg_1 |= (e->tCL - 1);
- } else {
+ else
timing->reg_1 |= (e->tCL + 2 - magic_number);
- }
+
timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10);
timing->reg_5 = (e->tRAS << 24 | e->tRC);
if (P->version == 1) {
timing->reg_2 |= magic_number << 24;
+
timing->reg_3 = (0x14 + e->tCL) << 24 |
- 0x16 << 16 |
- (e->tCL - 1) << 8 |
- (e->tCL - 1);
- timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13;
+ 0x16 << 16 |
+ (e->tCL - 1) << 8 |
+ (e->tCL - 1);
+
+ timing->reg_4 = (nv_rd32(dev, 0x10022c) & 0xffff0000) |
+ e->tUNK_13 << 8 | e->tUNK_13;
+
timing->reg_5 |= (e->tCL + 2) << 8;
+
timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16;
} else {
timing->reg_2 |= (unk19 - 1) << 24;
/* XXX: reg_10022c for recentish cards pretty much unknown*/
timing->reg_3 = e->tCL - 1;
timing->reg_4 = (unk20 << 24 | unk21 << 16 |
- e->tUNK_13 << 8 | e->tUNK_13);
+ e->tUNK_13 << 8 | e->tUNK_13);
/* XXX: +6? */
timing->reg_5 |= (unk19 + 6) << 8;
NV_DEBUG(dev, " 240: %08x\n", timing->reg_8);
}
-void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
- struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) {
- timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP);
- timing->reg_1 = (nv_rd32(dev,0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tCL & 0x0f);
- timing->reg_2 = (nv_rd32(dev,0x10f298) & 0xff0000ff) | e->tWR << 16 | e->tUNK_1 << 8;
+void nvc0_mem_timing_entry(struct drm_device *dev,
+ struct nouveau_pm_tbl_header *hdr,
+ struct nouveau_pm_tbl_entry *e,
+ struct nouveau_pm_memtiming *timing)
+{
+ timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 |
+ e->tRAS << 8 | e->tRP);
+
+ timing->reg_1 = (nv_rd32(dev, 0x10f294) & 0xff000000) |
+ (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) |
+ (e->tCL & 0x0f);
+
+ timing->reg_2 = (nv_rd32(dev, 0x10f298) & 0xff0000ff) |
+ e->tWR << 16 | e->tUNK_1 << 8;
+
timing->reg_3 = e->tUNK_20 << 9 | e->tUNK_13;
- timing->reg_4 = (nv_rd32(dev,0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15;
+
+ timing->reg_4 = (nv_rd32(dev, 0x10f2a0) & 0xfff000ff) |
+ e->tUNK_12 << 15;
+
NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id,
timing->reg_0, timing->reg_1,
timing->reg_2, timing->reg_3);
return;
if (P.version == 1)
- hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]);
+ hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev,
+ P.data[4]);
+ else if (P.version == 2)
+ hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev,
+ P.data[8]);
else
- if (P.version == 2)
- hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]);
- else {
NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
- }
} else {
NV_DEBUG(dev, "BMP version too old for memory\n");
return;
}
if (hdr->version != 0x10) {
- NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version);
+ NV_WARN(dev, "memory timing table 0x%02x unknown\n",
+ hdr->version);
return;
}
/* validate record length */
if (hdr->entry_len < 15) {
- NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len);
+ NV_ERROR(dev, "mem timing table length unknown: %d\n",
+ hdr->entry_len);
return;
}
/* parse vbios entries into common format */
- memtimings->timing =
- kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL);
+ memtimings->timing = kcalloc(hdr->entry_cnt,
+ sizeof(*memtimings->timing), GFP_KERNEL);
if (!memtimings->timing)
return;
/* Get "some number" from the timing reg for NV_40 and NV_50
* Used in calculations later... source unknown */
magic_number = 0;
- if (P.version == 1) {
+ if (P.version == 1)
magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24;
- }
- entry = (u8*) hdr + hdr->header_len;
+ entry = (u8 *) hdr + hdr->header_len;
for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) {
struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
+ struct nouveau_pm_tbl_entry *entry_struct =
+ (struct nouveau_pm_tbl_entry *) entry;
if (entry[0] == 0)
continue;
timing->WR = entry[0];
timing->CL = entry[2];
- if(dev_priv->card_type <= NV_40) {
- nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]);
- } else if(dev_priv->card_type == NV_50){
- nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]);
- } else if(dev_priv->card_type == NV_C0) {
- nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]);
+ if (dev_priv->card_type <= NV_40) {
+ nv40_mem_timing_entry(dev, hdr, entry_struct,
+ magic_number,
+ &pm->memtimings.timing[i]);
+ } else if (dev_priv->card_type == NV_50) {
+ nv50_mem_timing_entry(dev, &P, hdr, entry_struct,
+ magic_number,
+ &pm->memtimings.timing[i]);
+ } else if (dev_priv->card_type == NV_C0) {
+ nvc0_mem_timing_entry(dev, hdr, entry_struct,
+ &pm->memtimings.timing[i]);
}
}
memtimings->nr_timing = hdr->entry_cnt;
- memtimings->supported = P.version == 1;
+ memtimings->supported = (P.version == 1);
}
void
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
- if(mem->timing) {
- kfree(mem->timing);
- mem->timing = NULL;
+ kfree(mem->timing);
+ mem->timing = NULL;
+}
+
+int
+nouveau_mem_vbios_type(struct drm_device *dev)
+{
+ struct bit_entry M;
+ u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
+ if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
+ u8 *table = ROMPTR(dev, M.data[3]);
+ if (table && table[0] == 0x10 && ramcfg < table[3]) {
+ u8 *entry = table + table[1] + (ramcfg * table[2]);
+ switch (entry[0] & 0x0f) {
+ case 0: return NV_MEM_TYPE_DDR2;
+ case 1: return NV_MEM_TYPE_DDR3;
+ case 2: return NV_MEM_TYPE_GDDR3;
+ case 3: return NV_MEM_TYPE_GDDR5;
+ default:
+ break;
+ }
+
+ }
}
+ return NV_MEM_TYPE_UNKNOWN;
}
static int
projects / firefly-linux-kernel-4.4.55.git / blobdiff