Merge tag 'drm-intel-next-2015-09-11' of git://anongit.freedesktop.org/drm-intel...

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / intel_dp_mst.c

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 3e4be5a3becdddf9fd2a23e6be26f02da90a28f2..ff8ba55853be1cc6ef924a2c2ab2d15a1001634a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -39,7 +39,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
        struct intel_dp *intel_dp = &intel_dig_port->dp;
        struct drm_atomic_state *state;
        int bpp, i;
-       int lane_count, slots, rate;
+       int lane_count, slots;
        struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        struct drm_connector *drm_connector;
        struct intel_connector *connector, *found = NULL;
@@ -56,20 +56,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
         */
        lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 
-       rate = intel_dp_max_link_rate(intel_dp);
 
-       if (intel_dp->num_sink_rates) {
-               intel_dp->link_bw = 0;
-               intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
-       } else {
-               intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate);
-               intel_dp->rate_select = 0;
-       }
-
-       intel_dp->lane_count = lane_count;
+       pipe_config->lane_count = lane_count;
 
        pipe_config->pipe_bpp = 24;
-       pipe_config->port_clock = rate;
+       pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
 
        state = pipe_config->base.state;
 
@@ -184,6 +175,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
        if (intel_dp->active_mst_links == 0) {
                enum port port = intel_ddi_get_encoder_port(encoder);
 
+               intel_dp_set_link_params(intel_dp, intel_crtc->config);
+
                /* FIXME: add support for SKL */
                if (INTEL_INFO(dev)->gen < 9)
                        I915_WRITE(PORT_CLK_SEL(port),
@@ -286,6 +279,10 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
                break;
        }
        pipe_config->base.adjusted_mode.flags |= flags;
+
+       pipe_config->lane_count =
+               ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
        intel_dp_get_m_n(crtc, pipe_config);
 
        intel_ddi_clock_get(&intel_dig_port->base, pipe_config);