revert android-tegra-2.6.36-honeycomb-mr1-9001adc to v2.6.36

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 932a061f28d0d39f89fd94d2963f558c36efda53..979228594599a28ac7737762679f1c97fd5981bf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2044,11 +2044,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                                reg = I915_READ(trans_dp_ctl);
                                reg &= ~(TRANS_DP_PORT_SEL_MASK |
-                                        TRANS_DP_SYNC_MASK |
-                                        TRANS_DP_BPC_MASK);
+                                        TRANS_DP_SYNC_MASK);
                                reg |= (TRANS_DP_OUTPUT_ENABLE |
                                        TRANS_DP_ENH_FRAMING);
-                               reg |= TRANS_DP_8BPC;
 
                                if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
                                      reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
@@ -5675,13 +5673,6 @@ void intel_init_clock_gating(struct drm_device *dev)
 
                I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
 
-               /*
-                * On Ibex Peak and Cougar Point, we need to disable clock
-                * gating for the panel power sequencer or it will fail to
-                * start up when no ports are active.
-                */
-               I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
-
                /*
                 * According to the spec the following bits should be set in
                 * order to enable memory self-refresh