/* Clock gating state */
intel_init_clock_gating(dev);
- if (HAS_PCH_SPLIT(dev)) {
+ if (HAS_PCH_SPLIT(dev))
ironlake_enable_drps(dev);
- intel_init_emon(dev);
- }
/* Cache mode state */
I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);