MALI: rockchip: upgrade midgard DDK to r11p0-00rel0

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / arm / midgard / backend / gpu / mali_kbase_mmu_hw_direct.c

diff --git a/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_mmu_hw_direct.c b/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_mmu_hw_direct.c
index 4fd13e2de63e317679929feb9736e6a28a407743..c6c7b89712da3e92ba5c165cb0dfbd07fa66e6fb 100644 (file)
--- a/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_mmu_hw_direct.c
+++ b/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_mmu_hw_direct.c
@@ -1,6 +1,6 @@
 /*
  *
- * (C) COPYRIGHT 2014-2015 ARM Limited. All rights reserved.
+ * (C) COPYRIGHT 2014-2016 ARM Limited. All rights reserved.
  *
  * This program is free software and is provided to you under the terms of the
  * GNU General Public License version 2 as published by the Free Software
@@ -20,9 +20,7 @@
 #include <mali_kbase.h>
 #include <mali_kbase_mem.h>
 #include <mali_kbase_mmu_hw.h>
-#if defined(CONFIG_MALI_MIPE_ENABLED)
 #include <mali_kbase_tlstream.h>
-#endif
 #include <backend/gpu/mali_kbase_mmu_hw_direct.h>
 #include <backend/gpu/mali_kbase_device_internal.h>
 
@@ -165,6 +163,15 @@ void kbase_mmu_interrupt(struct kbase_device *kbdev, u32 irq_stat)
                                KBASE_MMU_FAULT_TYPE_BUS :
                                KBASE_MMU_FAULT_TYPE_PAGE;
 
+#ifdef CONFIG_MALI_GPU_MMU_AARCH64
+               as->fault_extra_addr = kbase_reg_read(kbdev,
+                               MMU_AS_REG(as_no, AS_FAULTEXTRA_HI),
+                               kctx);
+               as->fault_extra_addr <<= 32;
+               as->fault_extra_addr |= kbase_reg_read(kbdev,
+                               MMU_AS_REG(as_no, AS_FAULTEXTRA_LO),
+                               kctx);
+#endif /* CONFIG_MALI_GPU_MMU_AARCH64 */
 
                if (kbase_as_has_bus_fault(as)) {
                        /* Mark bus fault as handled.
@@ -203,10 +210,36 @@ void kbase_mmu_hw_configure(struct kbase_device *kbdev, struct kbase_as *as,
                struct kbase_context *kctx)
 {
        struct kbase_mmu_setup *current_setup = &as->current_setup;
-#ifdef CONFIG_MALI_MIPE_ENABLED
        u32 transcfg = 0;
-#endif
 
+#ifdef CONFIG_MALI_GPU_MMU_AARCH64
+       transcfg = current_setup->transcfg & 0xFFFFFFFFUL;
+
+       /* Set flag AS_TRANSCFG_PTW_MEMATTR_WRITE_BACK */
+       /* Clear PTW_MEMATTR bits */
+       transcfg &= ~AS_TRANSCFG_PTW_MEMATTR_MASK;
+       /* Enable correct PTW_MEMATTR bits */
+       transcfg |= AS_TRANSCFG_PTW_MEMATTR_WRITE_BACK;
+
+       if (kbdev->system_coherency == COHERENCY_ACE) {
+               /* Set flag AS_TRANSCFG_PTW_SH_OS (outer shareable) */
+               /* Clear PTW_SH bits */
+               transcfg = (transcfg & ~AS_TRANSCFG_PTW_SH_MASK);
+               /* Enable correct PTW_SH bits */
+               transcfg = (transcfg | AS_TRANSCFG_PTW_SH_OS);
+       }
+
+       kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSCFG_LO),
+                       transcfg, kctx);
+       kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSCFG_HI),
+                       (current_setup->transcfg >> 32) & 0xFFFFFFFFUL, kctx);
+
+#else /* CONFIG_MALI_GPU_MMU_AARCH64 */
+
+       if (kbdev->system_coherency == COHERENCY_ACE)
+               current_setup->transtab |= AS_TRANSTAB_LPAE_SHARE_OUTER;
+
+#endif /* CONFIG_MALI_GPU_MMU_AARCH64 */
 
        kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSTAB_LO),
                        current_setup->transtab & 0xFFFFFFFFUL, kctx);
@@ -218,12 +251,10 @@ void kbase_mmu_hw_configure(struct kbase_device *kbdev, struct kbase_as *as,
        kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_MEMATTR_HI),
                        (current_setup->memattr >> 32) & 0xFFFFFFFFUL, kctx);
 
-#if defined(CONFIG_MALI_MIPE_ENABLED)
        kbase_tlstream_tl_attrib_as_config(as,
                        current_setup->transtab,
                        current_setup->memattr,
                        transcfg);
-#endif
 
        write_cmd(kbdev, as->number, AS_COMMAND_UPDATE, kctx);
 }