static struct rockchip_ddr *ddr_data = NULL;
+static int _ddr_recalc_rate(void)
+{
+ int ddr_freq;
+
+ regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
+ &ddr_freq);
+ ddr_freq = ddr_freq * 2 * 1000000;
+ return ddr_freq;
+}
+
static int _ddr_change_freq(u32 n_mhz)
{
u32 ret;
printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
if (scpi_ddr_set_clk_rate(n_mhz))
pr_info("set ddr freq timeout\n");
- ret = scpi_ddr_get_clk_rate();
+ ret = _ddr_recalc_rate() / 1000000;
printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
return ret;
}
return (n_mhz / 12) * 12;
}
-static int _ddr_recalc_rate(void)
-{
- return (1000000 * scpi_ddr_get_clk_rate());
-}
-
static void _ddr_set_auto_self_refresh(bool en)
{
if (scpi_ddr_set_auto_self_refresh(en))
static void ddr_init(u32 dram_speed_bin, u32 freq)
{
- printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d\n"),
- __func__, dram_speed_bin, freq);
- if (scpi_ddr_init(dram_speed_bin, freq))
+ int lcdc_type;
+
+ lcdc_type = rockchip_get_screen_type();
+ printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
+ __func__, dram_speed_bin, freq, lcdc_type);
+ if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type))
pr_info("ddr init error\n");
else
printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
}
+static int ddr_init_resume(struct platform_device *pdev)
+{
+ ddr_init(DDR3_DEFAULT, 0);
+ return 0;
+}
+
static int __init rockchip_ddr_probe(struct platform_device *pdev)
{
struct device_node *np;
};
static struct platform_driver rockchip_ddr_driver = {
+#ifdef CONFIG_PM
+ .resume = ddr_init_resume,
+#endif /* CONFIG_PM */
.driver = {
.name = "rockchip_ddr",
.of_match_table = rockchip_ddr_of_match,