Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

[firefly-linux-kernel-4.4.55.git] / drivers / clk / spear / spear6xx_clock.c

diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index e862a333ad306166554098b919fc512ab51f13ae..9406f2426d64723f30764442eef1bb67ecac280a 100644 (file)
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -13,28 +13,27 @@
 #include <linux/clkdev.h>
 #include <linux/io.h>
 #include <linux/spinlock_types.h>
-#include <mach/misc_regs.h>
 #include "clk.h"
 
 static DEFINE_SPINLOCK(_lock);
 
-#define PLL1_CTR                       (MISC_BASE + 0x008)
-#define PLL1_FRQ                       (MISC_BASE + 0x00C)
-#define PLL2_CTR                       (MISC_BASE + 0x014)
-#define PLL2_FRQ                       (MISC_BASE + 0x018)
-#define PLL_CLK_CFG                    (MISC_BASE + 0x020)
+#define PLL1_CTR                       (misc_base + 0x008)
+#define PLL1_FRQ                       (misc_base + 0x00C)
+#define PLL2_CTR                       (misc_base + 0x014)
+#define PLL2_FRQ                       (misc_base + 0x018)
+#define PLL_CLK_CFG                    (misc_base + 0x020)
        /* PLL_CLK_CFG register masks */
        #define MCTR_CLK_SHIFT          28
        #define MCTR_CLK_MASK           3
 
-#define CORE_CLK_CFG                   (MISC_BASE + 0x024)
+#define CORE_CLK_CFG                   (misc_base + 0x024)
        /* CORE CLK CFG register masks */
        #define HCLK_RATIO_SHIFT        10
        #define HCLK_RATIO_MASK         2
        #define PCLK_RATIO_SHIFT        8
        #define PCLK_RATIO_MASK         2
 
-#define PERIP_CLK_CFG                  (MISC_BASE + 0x028)
+#define PERIP_CLK_CFG                  (misc_base + 0x028)
        /* PERIP_CLK_CFG register masks */
        #define CLCD_CLK_SHIFT          2
        #define CLCD_CLK_MASK           2
@@ -48,7 +47,7 @@ static DEFINE_SPINLOCK(_lock);
        #define GPT3_CLK_SHIFT          12
        #define GPT_CLK_MASK            1
 
-#define PERIP1_CLK_ENB                 (MISC_BASE + 0x02C)
+#define PERIP1_CLK_ENB                 (misc_base + 0x02C)
        /* PERIP1_CLK_ENB register masks */
        #define UART0_CLK_ENB           3
        #define UART1_CLK_ENB           4
@@ -74,13 +73,13 @@ static DEFINE_SPINLOCK(_lock);
        #define USBH0_CLK_ENB           25
        #define USBH1_CLK_ENB           26
 
-#define PRSC0_CLK_CFG                  (MISC_BASE + 0x044)
-#define PRSC1_CLK_CFG                  (MISC_BASE + 0x048)
-#define PRSC2_CLK_CFG                  (MISC_BASE + 0x04C)
+#define PRSC0_CLK_CFG                  (misc_base + 0x044)
+#define PRSC1_CLK_CFG                  (misc_base + 0x048)
+#define PRSC2_CLK_CFG                  (misc_base + 0x04C)
 
-#define CLCD_CLK_SYNT                  (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT                 (MISC_BASE + 0x060)
-#define UART_CLK_SYNT                  (MISC_BASE + 0x064)
+#define CLCD_CLK_SYNT                  (misc_base + 0x05C)
+#define FIRDA_CLK_SYNT                 (misc_base + 0x060)
+#define UART_CLK_SYNT                  (misc_base + 0x064)
 
 /* vco rate configuration table, in ascending order of rates */
 static struct pll_rate_tbl pll_rtbl[] = {
@@ -115,7 +114,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = {
        {.mscale = 1, .nscale = 0}, /* 83 MHz */
 };
 
-void __init spear6xx_clk_init(void)
+void __init spear6xx_clk_init(void __iomem *misc_base)
 {
        struct clk *clk, *clk1;