UPSTREAM: clk: rockchip: add new pll-type for rk3399 and similar socs

[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk.h

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 836e488989ad68bebaa017881cb542d2e8869a53..548970c4bab2c61296595c546689c5622366b43a 100644 (file)
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -88,6 +88,7 @@ enum rockchip_pll_type {
        pll_rk3036,
        pll_rk3066,
        pll_rk3366,
+       pll_rk3399,
 };
 
 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,     \
@@ -120,6 +121,18 @@ enum rockchip_pll_type {
        .nb = _nb,                                              \
 }
 
+#define RK3399_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,     \
+                       _postdiv2, _dsmpd, _frac)               \
+{                                                              \
+       .rate   = _rate##U,                                     \
+       .fbdiv = _fbdiv,                                        \
+       .postdiv1 = _postdiv1,                                  \
+       .refdiv = _refdiv,                                      \
+       .postdiv2 = _postdiv2,                                  \
+       .dsmpd = _dsmpd,                                        \
+       .frac = _frac,                                          \
+}
+
 /**
  * struct rockchip_clk_provider - information about clock provider
  * @reg_base: virtual address for the register base.
@@ -142,7 +155,7 @@ struct rockchip_pll_rate_table {
        unsigned int nf;
        unsigned int no;
        unsigned int nb;
-       /* for RK3036 */
+       /* for RK3036/RK3399 */
        unsigned int fbdiv;
        unsigned int postdiv1;
        unsigned int refdiv;