UPSTREAM: clk: rockchip: handle mux dependency of fractional dividers

[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk.h

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index dc8ecb2673b7b2a249befe3de93a4b39493f3134..17f33fb50f098dfb220cc145fec854f20fc00ac9 100644 (file)
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -2,6 +2,9 @@
  * Copyright (c) 2014 MundoReader S.L.
  * Author: Heiko Stuebner <heiko@sntech.de>
  *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng <zhengxing@rock-chips.com>
+ *
  * based on
  *
  * samsung/clk.h
@@ -30,7 +33,7 @@ struct clk;
 #define HIWORD_UPDATE(val, mask, shift) \
                ((val) << (shift) | (mask) << ((shift) + 16))
 
-/* register positions shared by RK2928, RK3066 and RK3188 */
+/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
 #define RK2928_PLL_CON(x)              ((x) * 0x4)
 #define RK2928_MODE_CON                0x40
 #define RK2928_CLKSEL_CON(x)   ((x) * 0x4 + 0x44)
@@ -40,6 +43,13 @@ struct clk;
 #define RK2928_SOFTRST_CON(x)  ((x) * 0x4 + 0x110)
 #define RK2928_MISC_CON                0x134
 
+#define RK3036_SDMMC_CON0              0x144
+#define RK3036_SDMMC_CON1              0x148
+#define RK3036_SDIO_CON0               0x14c
+#define RK3036_SDIO_CON1               0x150
+#define RK3036_EMMC_CON0               0x154
+#define RK3036_EMMC_CON1               0x158
+
 #define RK3288_PLL_CON(x)              RK2928_PLL_CON(x)
 #define RK3288_MODE_CON                        0x50
 #define RK3288_CLKSEL_CON(x)           ((x) * 0x4 + 0x60)
@@ -74,9 +84,23 @@ struct clk;
 #define RK3368_EMMC_CON1               0x41c
 
 enum rockchip_pll_type {
+       pll_rk3036,
        pll_rk3066,
+       pll_rk3366,
 };
 
+#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,     \
+                       _postdiv2, _dsmpd, _frac)               \
+{                                                              \
+       .rate   = _rate##U,                                     \
+       .fbdiv = _fbdiv,                                        \
+       .postdiv1 = _postdiv1,                                  \
+       .refdiv = _refdiv,                                      \
+       .postdiv2 = _postdiv2,                                  \
+       .dsmpd = _dsmpd,                                        \
+       .frac = _frac,                                          \
+}
+
 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)  \
 {                                              \
        .rate   = _rate##U,                     \
@@ -101,6 +125,13 @@ struct rockchip_pll_rate_table {
        unsigned int nf;
        unsigned int no;
        unsigned int nb;
+       /* for RK3036 */
+       unsigned int fbdiv;
+       unsigned int postdiv1;
+       unsigned int refdiv;
+       unsigned int postdiv2;
+       unsigned int dsmpd;
+       unsigned int frac;
 };
 
 /**
@@ -235,6 +266,7 @@ struct rockchip_clk_branch {
        int                             gate_offset;
        u8                              gate_shift;
        u8                              gate_flags;
+       struct rockchip_clk_branch      *child;
 };
 
 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
@@ -369,6 +401,24 @@ struct rockchip_clk_branch {
                .gate_flags     = gf,                           \
        }
 
+#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
+       {                                                       \
+               .id             = _id,                          \
+               .branch_type    = branch_fraction_divider,      \
+               .name           = cname,                        \
+               .parent_names   = (const char *[]){ pname },    \
+               .num_parents    = 1,                            \
+               .flags          = f,                            \
+               .muxdiv_offset  = mo,                           \
+               .div_shift      = 16,                           \
+               .div_width      = 16,                           \
+               .div_flags      = df,                           \
+               .gate_offset    = go,                           \
+               .gate_shift     = gs,                           \
+               .gate_flags     = gf,                           \
+               .child          = &(struct rockchip_clk_branch)ch, \
+       }
+
 #define MUX(_id, cname, pnames, f, o, s, w, mf)                        \
        {                                                       \
                .id             = _id,                          \