UPSTREAM: clk: rockchip: Add support for multiple clock providers

[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk-rk3368.c

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index b5c2c363da72db88fa9064a1c3e0da6d296e7a82..3a6add7f34bdcced44e1179b1e98354aca650730 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -856,6 +856,7 @@ static const char *const rk3368_critical_clocks[] __initconst = {
 
 static void __init rk3368_clk_init(struct device_node *np)
 {
+       struct rockchip_clk_provider *ctx;
        void __iomem *reg_base;
        struct clk *clk;
 
@@ -865,7 +866,11 @@ static void __init rk3368_clk_init(struct device_node *np)
                return;
        }
 
-       rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+       ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+       if (IS_ERR(ctx)) {
+               pr_err("%s: rockchip clk init failed\n", __func__);
+               return;
+       }
 
        /* xin12m is created by a cru-internal divider */
        clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
@@ -891,22 +896,22 @@ static void __init rk3368_clk_init(struct device_node *np)
                pr_warn("%s: could not register clock pclk_wdt: %ld\n",
                        __func__, PTR_ERR(clk));
        else
-               rockchip_clk_add_lookup(clk, PCLK_WDT);
+               rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
 
-       rockchip_clk_register_plls(rk3368_pll_clks,
+       rockchip_clk_register_plls(ctx, rk3368_pll_clks,
                                   ARRAY_SIZE(rk3368_pll_clks),
                                   RK3368_GRF_SOC_STATUS0);
-       rockchip_clk_register_branches(rk3368_clk_branches,
+       rockchip_clk_register_branches(ctx, rk3368_clk_branches,
                                  ARRAY_SIZE(rk3368_clk_branches));
        rockchip_clk_protect_critical(rk3368_critical_clocks,
                                      ARRAY_SIZE(rk3368_critical_clocks));
 
-       rockchip_clk_register_armclk(ARMCLKB, "armclkb",
+       rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
                        mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
                        &rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
                        ARRAY_SIZE(rk3368_cpuclkb_rates));
 
-       rockchip_clk_register_armclk(ARMCLKL, "armclkl",
+       rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
                        mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
                        &rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
                        ARRAY_SIZE(rk3368_cpuclkl_rates));
@@ -914,6 +919,8 @@ static void __init rk3368_clk_init(struct device_node *np)
        rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
                                  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
-       rockchip_register_restart_notifier(RK3368_GLB_SRST_FST, NULL);
+       rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);
+
+       rockchip_clk_of_add_provider(np, ctx);
 }
 CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);