FROMLIST: clk: rockchip: add clock flag parameter when register pll

[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk-pll.c

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 5f1edeedd17f102b49c33f7871e570078c143cb2..ddaf6ecdea3d2367f438108792f335d9909f65f1 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1224,7 +1224,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
                u8 num_parents, int con_offset, int grf_lock_offset,
                int lock_shift, int mode_offset, int mode_shift,
                struct rockchip_pll_rate_table *rate_table,
-               u8 clk_pll_flags)
+               unsigned long flags, u8 clk_pll_flags)
 {
        const char *pll_parents[3];
        struct clk_init_data init;
@@ -1280,7 +1280,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
        init.name = pll_name;
 
        /* keep all plls untouched for now */
-       init.flags = CLK_IGNORE_UNUSED;
+       init.flags = flags | CLK_IGNORE_UNUSED;
 
        init.parent_names = &parent_names[0];
        init.num_parents = 1;