clk: mvebu: extend common code to allow an optional refclk

[firefly-linux-kernel-4.4.55.git] / drivers / clk / mvebu / common.c

diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 0d4d1216f2dd25fb32f0b5417359d95957c9f086..15b370ff37481a61e4351377793d5619e14a6cd8 100644 (file)
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 
        /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
        clk_data.clk_num = 2 + desc->num_ratios;
+
+       /* One more clock for the optional refclk */
+       if (desc->get_refclk_freq)
+               clk_data.clk_num += 1;
+
        clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
                                GFP_KERNEL);
        if (WARN_ON(!clk_data.clks)) {
@@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
                WARN_ON(IS_ERR(clk_data.clks[2+n]));
        };
 
+       /* Register optional refclk */
+       if (desc->get_refclk_freq) {
+               const char *name = "refclk";
+               of_property_read_string_index(np, "clock-output-names",
+                                             2 + desc->num_ratios, &name);
+               rate = desc->get_refclk_freq(base);
+               clk_data.clks[2 + desc->num_ratios] =
+                       clk_register_fixed_rate(NULL, name, NULL,
+                                               CLK_IS_ROOT, rate);
+               WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
+       }
+
        /* SAR register isn't needed anymore */
        iounmap(base);