clk: rockchip: support setting ddr clock via SCPI APIs

[firefly-linux-kernel-4.4.55.git] / drivers / clk / clk-fixed-factor.c

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index fccabe497f6e5db42f6585acd9ecb1c4440bcb4e..83de57aeceea514dfaf53fc5a0271b1ca7d3b13d 100644 (file)
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -41,12 +41,11 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
 {
        struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                unsigned long best_parent;
 
                best_parent = (rate / fix->mult) * fix->div;
-               *prate = __clk_round_rate(__clk_get_parent(hw->clk),
-                               best_parent);
+               *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
        }
 
        return (*prate / fix->div) * fix->mult;