Uses different pass count for different parallel queue test cases
[libcds.git] / cds / urcu / details / gp.h
index eb43fc5f4a23258d1cf62c0525b0760b58e8df8e..b8173c4c1c65590dc1fc45c3048ecd75490fb777 100644 (file)
@@ -70,13 +70,7 @@ namespace cds { namespace urcu { namespace details {
             pRec->m_nAccessControl.store( gp_singleton<RCUtag>::instance()->global_control_word(atomics::memory_order_relaxed),
                 atomics::memory_order_relaxed );
 
-#   if CDS_COMPILER == CDS_COMPILER_CLANG && CDS_COMPILER_VERSION < 30800
-            // Seems, CLang 3.6-3.7 cannot handle acquire barrier correctly
-            CDS_COMPILER_RW_BARRIER;
-#   else
-            // acquire barrier
-            pRec->m_nAccessControl.load( atomics::memory_order_acquire );
-#   endif
+            atomics::atomic_thread_fence( atomics::memory_order_seq_cst );
         }
         else {
             // nested lock
@@ -93,6 +87,11 @@ namespace cds { namespace urcu { namespace details {
         uint32_t tmp = pRec->m_nAccessControl.load( atomics::memory_order_relaxed );
         assert( (tmp & rcu_class::c_nNestMask) > 0 );
 
+#if CDS_COMPILER == CDS_COMPILER_CLANG && CDS_COMPILER_VERSION < 30800
+        // CLang 3.6-3.7: some tests of intrusive::FeldmanHashSet based on general-purpose RCU
+        // are failed even in single-threaded mode (unit tests) without magic compiler barrier below
+        CDS_COMPILER_RW_BARRIER;
+#endif
         pRec->m_nAccessControl.store( tmp - 1, atomics::memory_order_release );
     }