rk: revert 20f3d0b+v3.0.66 to v3.0

[firefly-linux-kernel-4.4.55.git] / arch / x86 / kernel / cpu / mcheck / mce_amd.c

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index b97aa72702f17d6c80df9c3c93f7fff45ff9c425..bb0adad3514339d5a2f25d471af5f568f9b4d03e 100644 (file)
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -52,7 +52,6 @@ struct threshold_block {
        unsigned int            cpu;
        u32                     address;
        u16                     interrupt_enable;
-       bool                    interrupt_capable;
        u16                     threshold_limit;
        struct kobject          kobj;
        struct list_head        miscj;
@@ -65,9 +64,11 @@ struct threshold_bank {
 };
 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
 
+#ifdef CONFIG_SMP
 static unsigned char shared_bank[NR_BANKS] = {
        0, 0, 0, 0, 1
 };
+#endif
 
 static DEFINE_PER_CPU(unsigned char, bank_map);        /* see which banks are on */
 
@@ -85,21 +86,6 @@ struct thresh_restart {
        u16                     old_limit;
 };
 
-static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
-{
-       /*
-        * bank 4 supports APIC LVT interrupts implicitly since forever.
-        */
-       if (bank == 4)
-               return true;
-
-       /*
-        * IntP: interrupt present; if this bit is set, the thresholding
-        * bank can generate APIC LVT interrupts
-        */
-       return msr_high_bits & BIT(28);
-}
-
 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 {
        int msr = (hi & MASK_LVTOFF_HI) >> 20;
@@ -121,10 +107,8 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
        return 1;
 };
 
-/*
- * Called via smp_call_function_single(), must be called with correct
- * cpu affinity.
- */
+/* must be called with correct cpu affinity */
+/* Called via smp_call_function_single() */
 static void threshold_restart_bank(void *_tr)
 {
        struct thresh_restart *tr = _tr;
@@ -147,12 +131,6 @@ static void threshold_restart_bank(void *_tr)
                    (new_count & THRESHOLD_MAX);
        }
 
-       /* clear IntType */
-       hi &= ~MASK_INT_TYPE_HI;
-
-       if (!tr->b->interrupt_capable)
-               goto done;
-
        if (tr->set_lvt_off) {
                if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
                        /* set new lvt offset */
@@ -161,10 +139,9 @@ static void threshold_restart_bank(void *_tr)
                }
        }
 
-       if (tr->b->interrupt_enable)
-               hi |= INT_TYPE_APIC;
-
- done:
+       tr->b->interrupt_enable ?
+           (hi = (hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
+           (hi &= ~MASK_INT_TYPE_HI);
 
        hi |= MASK_COUNT_EN_HI;
        wrmsr(tr->b->address, lo, hi);
@@ -225,21 +202,18 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 
                        if (!block)
                                per_cpu(bank_map, cpu) |= (1 << bank);
-
+#ifdef CONFIG_SMP
                        if (shared_bank[bank] && c->cpu_core_id)
                                break;
+#endif
+                       offset = setup_APIC_mce(offset,
+                                               (high & MASK_LVTOFF_HI) >> 20);
 
                        memset(&b, 0, sizeof(b));
-                       b.cpu                   = cpu;
-                       b.bank                  = bank;
-                       b.block                 = block;
-                       b.address               = address;
-                       b.interrupt_capable     = lvt_interrupt_supported(bank, high);
-
-                       if (b.interrupt_capable) {
-                               int new = (high & MASK_LVTOFF_HI) >> 20;
-                               offset  = setup_APIC_mce(offset, new);
-                       }
+                       b.cpu           = cpu;
+                       b.bank          = bank;
+                       b.block         = block;
+                       b.address       = address;
 
                        mce_threshold_block_init(&b, offset);
                        mce_threshold_vector = amd_threshold_interrupt;
@@ -339,9 +313,6 @@ store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
        struct thresh_restart tr;
        unsigned long new;
 
-       if (!b->interrupt_capable)
-               return -EINVAL;
-
        if (strict_strtoul(buf, 0, &new) < 0)
                return -EINVAL;
 
@@ -500,7 +471,6 @@ static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
        b->cpu                  = cpu;
        b->address              = address;
        b->interrupt_enable     = 0;
-       b->interrupt_capable    = lvt_interrupt_supported(bank, high);
        b->threshold_limit      = THRESHOLD_MAX;
 
        INIT_LIST_HEAD(&b->miscj);