* Writes the command to the IOMMUs command buffer and informs the
* hardware about the new command.
*/
-static int iommu_queue_command_sync(struct amd_iommu *iommu,
- struct iommu_cmd *cmd,
- bool sync)
+static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
{
u32 left, tail, head, next_tail;
unsigned long flags;
copy_cmd_to_buffer(iommu, cmd, tail);
/* We need to sync now to make sure all commands are processed */
- iommu->need_sync = sync;
+ iommu->need_sync = true;
spin_unlock_irqrestore(&iommu->lock, flags);
return 0;
}
-static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
-{
- return iommu_queue_command_sync(iommu, cmd, true);
-}
-
/*
* This function queues a completion wait command into the command
* buffer of an IOMMU
build_completion_wait(&cmd, (u64)&sem);
- ret = iommu_queue_command_sync(iommu, &cmd, false);
+ ret = iommu_queue_command(iommu, &cmd);
if (ret)
return ret;
static void domain_flush_devices(struct protection_domain *domain)
{
struct iommu_dev_data *dev_data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&domain->lock, flags);
list_for_each_entry(dev_data, &domain->dev_list, list)
device_flush_dte(dev_data->dev);
+
+ spin_unlock_irqrestore(&domain->lock, flags);
}
/****************************************************************************
if (!pte || !IOMMU_PTE_PRESENT(*pte))
continue;
- dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
+ dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
}
update_domain(&dma_dom->domain);