tile: parameterize VA and PA space more cleanly

[firefly-linux-kernel-4.4.55.git] / arch / tile / kernel / intvec_64.S

diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
index df19d4f3946ee391ef255f3ce2c0cc2dd6fa9c83..c3a2335fa6a8b7aca1628a35dce2217762089446 100644 (file)
--- a/arch/tile/kernel/intvec_64.S
+++ b/arch/tile/kernel/intvec_64.S
@@ -34,6 +34,16 @@
 
 #define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
 
+#if CONFIG_KERNEL_PL == 1 || CONFIG_KERNEL_PL == 2
+/*
+ * Set "result" non-zero if ex1 holds the PL of the kernel
+ * (with or without ICS being set).  Note this works only
+ * because we never find the PL at level 3.
+ */
+# define IS_KERNEL_EX1(result, ex1) andi result, ex1, CONFIG_KERNEL_PL
+#else
+# error Recode IS_KERNEL_EX1 for CONFIG_KERNEL_PL
+#endif
 
        .macro  push_reg reg, ptr=sp, delta=-8
        {
@@ -132,13 +142,9 @@ intvec_\vecname:
        mfspr   r3, SPR_SYSTEM_SAVE_K_0
 
        /* Get &thread_info->unalign_jit_tmp[0] in r3. */
+       bfexts  r3, r3, 0, CPU_SHIFT-1
        mm      r3, zero, LOG2_THREAD_SIZE, 63
-#if THREAD_SIZE < 65536
-       addli   r3, r3, -(PAGE_SIZE - THREAD_INFO_UNALIGN_JIT_TMP_OFFSET)
-#else
-       addli   r3, r3, -(PAGE_SIZE/2)
-       addli   r3, r3, -(PAGE_SIZE/2 - THREAD_INFO_UNALIGN_JIT_TMP_OFFSET)
-#endif
+       addli   r3, r3, THREAD_INFO_UNALIGN_JIT_TMP_OFFSET
 
        /*
         * Save r0, r1, r2 into thread_info array r3 points to
@@ -312,7 +318,7 @@ intvec_\vecname:
         */
        {
         blbs   sp, 2f
-        andi   r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
+        IS_KERNEL_EX1(r0, r0)
        }
 
        .ifc    \vecnum, INT_DOUBLE_FAULT
@@ -365,13 +371,13 @@ intvec_\vecname:
 
 2:
        /*
-        * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
-        * the current stack top in the higher bits.  So we recover
-        * our stack top by just masking off the low bits, then
+        * SYSTEM_SAVE_K_0 holds the cpu number in the high bits, and
+        * the current stack top in the lower bits.  So we recover
+        * our starting stack value by sign-extending the low bits, then
         * point sp at the top aligned address on the actual stack page.
         */
        mfspr   r0, SPR_SYSTEM_SAVE_K_0
-       mm      r0, zero, LOG2_THREAD_SIZE, 63
+       bfexts  r0, r0, 0, CPU_SHIFT-1
 
 0:
        /*
@@ -393,6 +399,9 @@ intvec_\vecname:
         *    cache line 1: r6...r13
         *    cache line 0: 2 x frame, r0..r5
         */
+#if STACK_TOP_DELTA != 64
+#error STACK_TOP_DELTA must be 64 for assumptions here and in task_pt_regs()
+#endif
        andi    r0, r0, -64
 
        /*
@@ -526,7 +535,7 @@ intvec_\vecname:
 #ifdef __COLLECT_LINKER_FEEDBACK__
        .pushsection .text.intvec_feedback,"ax"
        .org    (\vecnum << 5)
-       FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
+       FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt, 1 << 8)
        jrp     lr
        .popsection
 #endif
@@ -642,11 +651,12 @@ intvec_\vecname:
        /*
         * If we will be returning to the kernel, we will need to
         * reset the interrupt masks to the state they had before.
-        * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
+        * Set DISABLE_IRQ in flags iff we came from kernel pl with
+        * irqs disabled.
         */
        mfspr   r32, SPR_EX_CONTEXT_K_1
        {
-        andi   r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
+        IS_KERNEL_EX1(r22, r22)
         PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
        }
        beqzt   r32, 1f       /* zero if from user space */
@@ -690,7 +700,7 @@ intvec_\vecname:
        }
        {
         shl16insli r21, r21, hw1(__per_cpu_offset)
-        bfextu r20, r20, 0, LOG2_THREAD_SIZE-1
+        bfextu r20, r20, CPU_SHIFT, 63
        }
        shl16insli r21, r21, hw0(__per_cpu_offset)
        shl3add r20, r20, r21
@@ -813,7 +823,7 @@ STD_ENTRY(interrupt_return)
         PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
        }
        ld      r29, r29
-       andi    r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
+       IS_KERNEL_EX1(r29, r29)
        {
         beqzt  r29, .Lresume_userspace
         move   r29, sp
@@ -937,7 +947,7 @@ STD_ENTRY(interrupt_return)
         PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
        }
        {
-        andi   r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
+        IS_KERNEL_EX1(r0, r0)
         ld     r32, r32
        }
        bnez    r0, 1f
@@ -1008,7 +1018,7 @@ STD_ENTRY(interrupt_return)
        pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
        {
         mtspr  SPR_EX_CONTEXT_K_1, lr
-        andi   lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
+        IS_KERNEL_EX1(lr, lr)
        }
        {
         mtspr  SPR_EX_CONTEXT_K_0, r21
@@ -1475,8 +1485,10 @@ STD_ENTRY(fill_ra_stack)
                __int_hand   \vecnum, \vecname, \c_routine, \processing
        .endm
 
-/* Include .intrpt1 array of interrupt vectors */
-       .section ".intrpt1", "ax"
+/* Include .intrpt array of interrupt vectors */
+       .section ".intrpt", "ax"
+       .global intrpt_start
+intrpt_start:
 
 #define op_handle_perf_interrupt bad_intr
 #define op_handle_aux_perf_interrupt bad_intr