#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
+#include <linux/bootmem.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/cpudata.h>
#include <asm/auxio.h>
+#include <asm/head.h>
#ifdef CONFIG_SMP
static void distribute_irqs(void);
* access to this structure takes a TLB miss it could cause
* the 5-level sparc v9 trap stack to overflow.
*/
-struct irq_work_struct {
- unsigned int irq_worklists[16];
-};
-struct irq_work_struct __irq_work[NR_CPUS];
-#define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
+#define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
-static struct irqaction *irq_action[NR_IRQS+1];
+static struct irqaction *irq_action[NR_IRQS];
/* This only synchronizes entities which modify IRQ handler
* state and some selected user-level spots that want to
*/
#define put_ino_in_irqaction(action, irq) \
action->flags &= 0xffffffffffffUL; \
- if (__bucket(irq) == &pil0_dummy_bucket) \
- action->flags |= 0xdeadUL << 48; \
- else \
- action->flags |= __irq_ino(irq) << 48;
+ action->flags |= __irq_ino(irq) << 48;
+
#define get_ino_in_irqaction(action) (action->flags >> 48)
#define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
#ifndef CONFIG_SMP
seq_printf(p, "%10u ", kstat_irqs(i));
#else
- for (j = 0; j < NR_CPUS; j++) {
- if (!cpu_online(j))
- continue;
+ for_each_online_cpu(j) {
seq_printf(p, "%10u ",
kstat_cpu(j).irqs[i]);
}
#endif
- seq_printf(p, " %s:%lx", action->name,
- get_ino_in_irqaction(action));
- for (action = action->next; action; action = action->next) {
- seq_printf(p, ", %s:%lx", action->name,
- get_ino_in_irqaction(action));
- }
+ seq_printf(p, " %s", action->name);
+ for (action = action->next; action; action = action->next)
+ seq_printf(p, ", %s", action->name);
seq_putc(p, '\n');
}
out_unlock:
return 0;
}
+extern unsigned long real_hard_smp_processor_id(void);
+
+static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
+{
+ unsigned int tid;
+
+ if (this_is_starfire) {
+ tid = starfire_translate(imap, cpuid);
+ tid <<= IMAP_TID_SHIFT;
+ tid &= IMAP_TID_UPA;
+ } else {
+ if (tlb_type == cheetah || tlb_type == cheetah_plus) {
+ unsigned long ver;
+
+ __asm__ ("rdpr %%ver, %0" : "=r" (ver));
+ if ((ver >> 32UL) == __JALAPENO_ID ||
+ (ver >> 32UL) == __SERRANO_ID) {
+ tid = cpuid << IMAP_TID_SHIFT;
+ tid &= IMAP_TID_JBUS;
+ } else {
+ unsigned int a = cpuid & 0x1f;
+ unsigned int n = (cpuid >> 5) & 0x1f;
+
+ tid = ((a << IMAP_AID_SHIFT) |
+ (n << IMAP_NID_SHIFT));
+ tid &= (IMAP_AID_SAFARI |
+ IMAP_NID_SAFARI);;
+ }
+ } else {
+ tid = cpuid << IMAP_TID_SHIFT;
+ tid &= IMAP_TID_UPA;
+ }
+ }
+
+ return tid;
+}
+
/* Now these are always passed a true fully specified sun4u INO. */
void enable_irq(unsigned int irq)
{
struct ino_bucket *bucket = __bucket(irq);
- unsigned long imap;
- unsigned long tid;
+ unsigned long imap, cpuid;
imap = bucket->imap;
if (imap == 0UL)
preempt_disable();
- if (tlb_type == cheetah || tlb_type == cheetah_plus) {
- unsigned long ver;
-
- __asm__ ("rdpr %%ver, %0" : "=r" (ver));
- if ((ver >> 32) == 0x003e0016) {
- /* We set it to our JBUS ID. */
- __asm__ __volatile__("ldxa [%%g0] %1, %0"
- : "=r" (tid)
- : "i" (ASI_JBUS_CONFIG));
- tid = ((tid & (0x1fUL<<17)) << 9);
- tid &= IMAP_TID_JBUS;
- } else {
- /* We set it to our Safari AID. */
- __asm__ __volatile__("ldxa [%%g0] %1, %0"
- : "=r" (tid)
- : "i" (ASI_SAFARI_CONFIG));
- tid = ((tid & (0x3ffUL<<17)) << 9);
- tid &= IMAP_AID_SAFARI;
- }
- } else if (this_is_starfire == 0) {
- /* We set it to our UPA MID. */
- __asm__ __volatile__("ldxa [%%g0] %1, %0"
- : "=r" (tid)
- : "i" (ASI_UPA_CONFIG));
- tid = ((tid & UPA_CONFIG_MID) << 9);
- tid &= IMAP_TID_UPA;
+ /* This gets the physical processor ID, even on uniprocessor,
+ * so we can always program the interrupt target correctly.
+ */
+ cpuid = real_hard_smp_processor_id();
+
+ if (tlb_type == hypervisor) {
+ unsigned int ino = __irq_ino(irq);
+ int err;
+
+ err = sun4v_intr_settarget(ino, cpuid);
+ if (err != HV_EOK)
+ printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
+ ino, cpuid, err);
+ err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
+ if (err != HV_EOK)
+ printk("sun4v_intr_setenabled(%x): err(%d)\n",
+ ino, err);
} else {
- tid = (starfire_translate(imap, smp_processor_id()) << 26);
- tid &= IMAP_TID_UPA;
+ unsigned int tid = sun4u_compute_tid(imap, cpuid);
+
+ /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
+ * of this SYSIO's preconfigured IGN in the SYSIO Control
+ * Register, the hardware just mirrors that value here.
+ * However for Graphics and UPA Slave devices the full
+ * IMAP_INR field can be set by the programmer here.
+ *
+ * Things like FFB can now be handled via the new IRQ
+ * mechanism.
+ */
+ upa_writel(tid | IMAP_VALID, imap);
}
- /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
- * of this SYSIO's preconfigured IGN in the SYSIO Control
- * Register, the hardware just mirrors that value here.
- * However for Graphics and UPA Slave devices the full
- * IMAP_INR field can be set by the programmer here.
- *
- * Things like FFB can now be handled via the new IRQ mechanism.
- */
- upa_writel(tid | IMAP_VALID, imap);
-
preempt_enable();
}
imap = bucket->imap;
if (imap != 0UL) {
- u32 tmp;
+ if (tlb_type == hypervisor) {
+ unsigned int ino = __irq_ino(irq);
+ int err;
+
+ err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
+ if (err != HV_EOK)
+ printk("sun4v_intr_setenabled(%x): "
+ "err(%d)\n", ino, err);
+ } else {
+ u32 tmp;
- /* NOTE: We do not want to futz with the IRQ clear registers
- * and move the state to IDLE, the SCSI code does call
- * disable_irq() to assure atomicity in the queue cmd
- * SCSI adapter driver code. Thus we'd lose interrupts.
- */
- tmp = upa_readl(imap);
- tmp &= ~IMAP_VALID;
- upa_writel(tmp, imap);
+ /* NOTE: We do not want to futz with the IRQ clear registers
+ * and move the state to IDLE, the SCSI code does call
+ * disable_irq() to assure atomicity in the queue cmd
+ * SCSI adapter driver code. Thus we'd lose interrupts.
+ */
+ tmp = upa_readl(imap);
+ tmp &= ~IMAP_VALID;
+ upa_writel(tmp, imap);
+ }
}
}
-/* The timer is the one "weird" interrupt which is generated by
- * the CPU %tick register and not by some normal vectored interrupt
- * source. To handle this special case, we use this dummy INO bucket.
- */
-static struct irq_desc pil0_dummy_desc;
-static struct ino_bucket pil0_dummy_bucket = {
- .irq_info = &pil0_dummy_desc,
-};
-
-static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
+static void build_irq_error(const char *msg, unsigned int ino, int inofixup,
unsigned long iclr, unsigned long imap,
struct ino_bucket *bucket)
{
- prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
- "(%d:%d:%016lx:%016lx), halting...\n",
- ino, bucket->pil, bucket->iclr, bucket->imap,
- pil, inofixup, iclr, imap);
+ prom_printf("IRQ: INO %04x (%016lx:%016lx) --> "
+ "(%d:%016lx:%016lx), halting...\n",
+ ino, bucket->iclr, bucket->imap,
+ inofixup, iclr, imap);
prom_halt();
}
-unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
+unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
{
struct ino_bucket *bucket;
int ino;
- if (pil == 0) {
- if (iclr != 0UL || imap != 0UL) {
- prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
- iclr, imap);
- prom_halt();
- }
- return __irq(&pil0_dummy_bucket);
- }
+ BUG_ON(tlb_type == hypervisor);
/* RULE: Both must be specified in all other cases. */
if (iclr == 0UL || imap == 0UL) {
- prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
- pil, inofixup, iclr, imap);
+ prom_printf("Invalid build_irq %d %016lx %016lx\n",
+ inofixup, iclr, imap);
prom_halt();
}
ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
if (ino > NUM_IVECS) {
- prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
- ino, pil, inofixup, iclr, imap);
+ prom_printf("Invalid INO %04x (%d:%016lx:%016lx)\n",
+ ino, inofixup, iclr, imap);
prom_halt();
}
bucket = &ivector_table[ino];
if (bucket->flags & IBF_ACTIVE)
build_irq_error("IRQ: Trying to build active INO bucket.\n",
- ino, pil, inofixup, iclr, imap, bucket);
+ ino, inofixup, iclr, imap, bucket);
if (bucket->irq_info) {
if (bucket->imap != imap || bucket->iclr != iclr)
build_irq_error("IRQ: Trying to reinit INO bucket.\n",
- ino, pil, inofixup, iclr, imap, bucket);
+ ino, inofixup, iclr, imap, bucket);
goto out;
}
- bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
+ bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
if (!bucket->irq_info) {
prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
prom_halt();
}
- memset(bucket->irq_info, 0, sizeof(struct irq_desc));
/* Ok, looks good, set it up. Don't touch the irq_chain or
* the pending flag.
*/
bucket->imap = imap;
bucket->iclr = iclr;
- bucket->pil = pil;
bucket->flags = 0;
out:
return __irq(bucket);
}
+unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, unsigned char flags)
+{
+ struct ino_bucket *bucket;
+ unsigned long sysino;
+
+ sysino = sun4v_devino_to_sysino(devhandle, devino);
+
+ bucket = &ivector_table[sysino];
+
+ /* Catch accidental accesses to these things. IMAP/ICLR handling
+ * is done by hypervisor calls on sun4v platforms, not by direct
+ * register accesses.
+ *
+ * But we need to make them look unique for the disable_irq() logic
+ * in free_irq().
+ */
+ bucket->imap = ~0UL - sysino;
+ bucket->iclr = ~0UL - sysino;
+
+ bucket->flags = flags;
+
+ bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
+ if (!bucket->irq_info) {
+ prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
+ prom_halt();
+ }
+
+ return __irq(bucket);
+}
+
static void atomic_bucket_insert(struct ino_bucket *bucket)
{
unsigned long pstate;
__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
__asm__ __volatile__("wrpr %0, %1, %%pstate"
: : "r" (pstate), "i" (PSTATE_IE));
- ent = irq_work(smp_processor_id(), bucket->pil);
+ ent = irq_work(smp_processor_id());
bucket->irq_chain = *ent;
*ent = __irq(bucket);
__asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
static int check_irq_sharing(int pil, unsigned long irqflags)
{
- struct irqaction *action, *tmp;
+ struct irqaction *action;
action = *(irq_action + pil);
if (action) {
- if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
- for (tmp = action; tmp->next; tmp = tmp->next)
- ;
- } else {
+ if (!(action->flags & SA_SHIRQ) || !(irqflags & SA_SHIRQ))
return -EBUSY;
- }
}
return 0;
}
if (unlikely(!bucket->irq_info))
return -ENODEV;
- if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
+ if (irqflags & SA_SAMPLE_RANDOM) {
/*
* This function might sleep, we want to call it first,
* outside of the atomic block. In SA_STATIC_ALLOC case,
* installing a new handler, but is this really a problem,
* only the sysadmin is able to do this.
*/
- rand_initialize_irq(irq);
+ rand_initialize_irq(PIL_DEVICE_IRQ);
}
spin_lock_irqsave(&irq_action_lock, flags);
- if (check_irq_sharing(bucket->pil, irqflags)) {
+ if (check_irq_sharing(PIL_DEVICE_IRQ, irqflags)) {
spin_unlock_irqrestore(&irq_action_lock, flags);
return -EBUSY;
}
}
bucket->flags |= IBF_ACTIVE;
- pending = 0;
- if (bucket != &pil0_dummy_bucket) {
- pending = bucket->pending;
- if (pending)
- bucket->pending = 0;
- }
+ pending = bucket->pending;
+ if (pending)
+ bucket->pending = 0;
action->handler = handler;
action->flags = irqflags;
put_ino_in_irqaction(action, irq);
put_smpaff_in_irqaction(action, CPU_MASK_NONE);
- append_irq_action(bucket->pil, action);
+ append_irq_action(PIL_DEVICE_IRQ, action);
enable_irq(irq);
/* We ate the IVEC already, this makes sure it does not get lost. */
if (pending) {
atomic_bucket_insert(bucket);
- set_softint(1 << bucket->pil);
+ set_softint(1 << PIL_DEVICE_IRQ);
}
spin_unlock_irqrestore(&irq_action_lock, flags);
- if (bucket != &pil0_dummy_bucket)
- register_irq_proc(__irq_ino(irq));
+ register_irq_proc(__irq_ino(irq));
#ifdef CONFIG_SMP
distribute_irqs();
static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
{
- struct ino_bucket *bucket = __bucket(irq);
struct irqaction *action, **pp;
- pp = irq_action + bucket->pil;
+ pp = irq_action + PIL_DEVICE_IRQ;
action = *pp;
if (unlikely(!action))
return NULL;
if (unlikely(!action->handler)) {
- printk("Freeing free IRQ %d\n", bucket->pil);
+ printk("Freeing free IRQ %d\n", PIL_DEVICE_IRQ);
return NULL;
}
{
struct irqaction *action;
struct ino_bucket *bucket;
+ struct irq_desc *desc;
unsigned long flags;
+ int ent, i;
spin_lock_irqsave(&irq_action_lock, flags);
spin_lock_irqsave(&irq_action_lock, flags);
bucket = __bucket(irq);
- if (bucket != &pil0_dummy_bucket) {
- struct irq_desc *desc = bucket->irq_info;
- unsigned long imap = bucket->imap;
- int ent, i;
+ desc = bucket->irq_info;
- for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
- struct irqaction *p = &desc->action[i];
+ for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
+ struct irqaction *p = &desc->action[i];
- if (p == action) {
- desc->action_active_mask &= ~(1 << i);
- break;
- }
+ if (p == action) {
+ desc->action_active_mask &= ~(1 << i);
+ break;
}
+ }
- if (!desc->action_active_mask) {
- /* This unique interrupt source is now inactive. */
- bucket->flags &= ~IBF_ACTIVE;
+ if (!desc->action_active_mask) {
+ unsigned long imap = bucket->imap;
- /* See if any other buckets share this bucket's IMAP
- * and are still active.
- */
- for (ent = 0; ent < NUM_IVECS; ent++) {
- struct ino_bucket *bp = &ivector_table[ent];
- if (bp != bucket &&
- bp->imap == imap &&
- (bp->flags & IBF_ACTIVE) != 0)
- break;
- }
+ /* This unique interrupt source is now inactive. */
+ bucket->flags &= ~IBF_ACTIVE;
- /* Only disable when no other sub-irq levels of
- * the same IMAP are active.
- */
- if (ent == NUM_IVECS)
- disable_irq(irq);
+ /* See if any other buckets share this bucket's IMAP
+ * and are still active.
+ */
+ for (ent = 0; ent < NUM_IVECS; ent++) {
+ struct ino_bucket *bp = &ivector_table[ent];
+ if (bp != bucket &&
+ bp->imap == imap &&
+ (bp->flags & IBF_ACTIVE) != 0)
+ break;
}
+
+ /* Only disable when no other sub-irq levels of
+ * the same IMAP are active.
+ */
+ if (ent == NUM_IVECS)
+ disable_irq(irq);
}
spin_unlock_irqrestore(&irq_action_lock, flags);
}
#endif /* CONFIG_SMP */
-static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
+static void process_bucket(struct ino_bucket *bp, struct pt_regs *regs)
{
struct irq_desc *desc = bp->irq_info;
unsigned char flags = bp->flags;
if (!action_mask)
break;
}
- if (bp->pil != 0) {
+
+ if (tlb_type == hypervisor) {
+ unsigned int ino = __irq_ino(bp);
+ int err;
+
+ err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
+ if (err != HV_EOK)
+ printk("sun4v_intr_setstate(%x): "
+ "err(%d)\n", ino, err);
+ } else {
upa_writel(ICLR_IDLE, bp->iclr);
- /* Test and add entropy */
- if (random & SA_SAMPLE_RANDOM)
- add_interrupt_randomness(irq);
}
+
+ /* Test and add entropy */
+ if (random & SA_SAMPLE_RANDOM)
+ add_interrupt_randomness(PIL_DEVICE_IRQ);
out:
bp->flags &= ~IBF_INPROGRESS;
}
+#ifndef CONFIG_SMP
+extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
+
+void timer_irq(int irq, struct pt_regs *regs)
+{
+ unsigned long clr_mask = 1 << irq;
+ unsigned long tick_mask = tick_ops->softint_mask;
+
+ if (get_softint() & tick_mask) {
+ irq = 0;
+ clr_mask = tick_mask;
+ }
+ clear_softint(clr_mask);
+
+ irq_enter();
+ kstat_this_cpu.irqs[irq]++;
+ timer_interrupt(irq, NULL, regs);
+ irq_exit();
+}
+#endif
+
void handler_irq(int irq, struct pt_regs *regs)
{
struct ino_bucket *bp;
int cpu = smp_processor_id();
-#ifndef CONFIG_SMP
- /*
- * Check for TICK_INT on level 14 softint.
+ /* XXX at this point we should be able to assert that
+ * XXX irq is PIL_DEVICE_IRQ...
*/
- {
- unsigned long clr_mask = 1 << irq;
- unsigned long tick_mask = tick_ops->softint_mask;
-
- if ((irq == 14) && (get_softint() & tick_mask)) {
- irq = 0;
- clr_mask = tick_mask;
- }
- clear_softint(clr_mask);
- }
-#else
clear_softint(1 << irq);
-#endif
irq_enter();
- kstat_this_cpu.irqs[irq]++;
/* Sliiiick... */
-#ifndef CONFIG_SMP
- bp = ((irq != 0) ?
- __bucket(xchg32(irq_work(cpu, irq), 0)) :
- &pil0_dummy_bucket);
-#else
- bp = __bucket(xchg32(irq_work(cpu, irq), 0));
-#endif
+ bp = __bucket(xchg32(irq_work(cpu), 0));
while (bp) {
struct ino_bucket *nbp = __bucket(bp->irq_chain);
+ kstat_this_cpu.irqs[bp->virt_irq]++;
+
bp->irq_chain = 0;
- process_bucket(irq, bp, regs);
+ process_bucket(bp, regs);
bp = nbp;
}
irq_exit();
}
#ifdef CONFIG_BLK_DEV_FD
-extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
+extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);
/* XXX No easy way to include asm/floppy.h XXX */
extern unsigned char *pdma_vaddr;
val = readb(auxio_register);
val |= AUXIO_AUX1_FTCNT;
writeb(val, auxio_register);
- val &= AUXIO_AUX1_FTCNT;
+ val &= ~AUXIO_AUX1_FTCNT;
writeb(val, auxio_register);
doing_pdma = 0;
static int retarget_one_irq(struct irqaction *p, int goal_cpu)
{
struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
- unsigned long imap = bucket->imap;
- unsigned int tid;
while (!cpu_online(goal_cpu)) {
if (++goal_cpu >= NR_CPUS)
goal_cpu = 0;
}
- if (tlb_type == cheetah || tlb_type == cheetah_plus) {
- tid = goal_cpu << 26;
- tid &= IMAP_AID_SAFARI;
- } else if (this_is_starfire == 0) {
- tid = goal_cpu << 26;
- tid &= IMAP_TID_UPA;
+ if (tlb_type == hypervisor) {
+ unsigned int ino = __irq_ino(bucket);
+
+ sun4v_intr_settarget(ino, goal_cpu);
+ sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
} else {
- tid = (starfire_translate(imap, goal_cpu) << 26);
- tid &= IMAP_TID_UPA;
+ unsigned long imap = bucket->imap;
+ unsigned int tid = sun4u_compute_tid(imap, goal_cpu);
+
+ upa_writel(tid | IMAP_VALID, imap);
}
- upa_writel(tid | IMAP_VALID, imap);
do {
if (++goal_cpu >= NR_CPUS)
spin_lock_irqsave(&irq_action_lock, flags);
cpu = 0;
- /*
- * Skip the timer at [0], and very rare error/power intrs at [15].
- * Also level [12], it causes problems on Ex000 systems.
- */
for (level = 1; level < NR_IRQS; level++) {
struct irqaction *p = irq_action[level];
- if (level == 12)
- continue;
-
while(p) {
cpu = retarget_one_irq(p, cpu);
p = p->next;
void init_irqwork_curcpu(void)
{
- register struct irq_work_struct *workp asm("o2");
- register unsigned long tmp asm("o3");
int cpu = hard_smp_processor_id();
- memset(__irq_work + cpu, 0, sizeof(*workp));
-
- /* Make sure we are called with PSTATE_IE disabled. */
- __asm__ __volatile__("rdpr %%pstate, %0\n\t"
- : "=r" (tmp));
- if (tmp & PSTATE_IE) {
- prom_printf("BUG: init_irqwork_curcpu() called with "
- "PSTATE_IE enabled, bailing.\n");
- __asm__ __volatile__("mov %%i7, %0\n\t"
- : "=r" (tmp));
- prom_printf("BUG: Called from %lx\n", tmp);
+ trap_block[cpu].irq_worklist = 0;
+}
+
+static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
+{
+ unsigned long num_entries = 128;
+ unsigned long status;
+
+ status = sun4v_cpu_qconf(type, paddr, num_entries);
+ if (status != HV_EOK) {
+ prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
+ "err %lu\n", type, paddr, num_entries, status);
prom_halt();
}
+}
- /* Set interrupt globals. */
- workp = &__irq_work[cpu];
- __asm__ __volatile__(
- "rdpr %%pstate, %0\n\t"
- "wrpr %0, %1, %%pstate\n\t"
- "mov %2, %%g6\n\t"
- "wrpr %0, 0x0, %%pstate\n\t"
- : "=&r" (tmp)
- : "i" (PSTATE_IG), "r" (workp));
+static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
+{
+ struct trap_per_cpu *tb = &trap_block[this_cpu];
+
+ register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
+ register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
+ register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
+ register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
+}
+
+static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
+{
+ void *page;
+
+ if (use_bootmem)
+ page = alloc_bootmem_low_pages(PAGE_SIZE);
+ else
+ page = (void *) get_zeroed_page(GFP_ATOMIC);
+
+ if (!page) {
+ prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
+ prom_halt();
+ }
+
+ *pa_ptr = __pa(page);
+}
+
+static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
+{
+ void *page;
+
+ if (use_bootmem)
+ page = alloc_bootmem_low_pages(PAGE_SIZE);
+ else
+ page = (void *) get_zeroed_page(GFP_ATOMIC);
+
+ if (!page) {
+ prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
+ prom_halt();
+ }
+
+ *pa_ptr = __pa(page);
+}
+
+static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
+{
+#ifdef CONFIG_SMP
+ void *page;
+
+ BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
+
+ if (use_bootmem)
+ page = alloc_bootmem_low_pages(PAGE_SIZE);
+ else
+ page = (void *) get_zeroed_page(GFP_ATOMIC);
+
+ if (!page) {
+ prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
+ prom_halt();
+ }
+
+ tb->cpu_mondo_block_pa = __pa(page);
+ tb->cpu_list_pa = __pa(page + 64);
+#endif
+}
+
+/* Allocate and register the mondo and error queues for this cpu. */
+void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
+{
+ struct trap_per_cpu *tb = &trap_block[cpu];
+
+ if (alloc) {
+ alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
+ alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
+ alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
+ alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
+ alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
+ alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
+
+ init_cpu_send_mondo_info(tb, use_bootmem);
+ }
+
+ if (load) {
+ if (cpu != hard_smp_processor_id()) {
+ prom_printf("SUN4V: init mondo on cpu %d not %d\n",
+ cpu, hard_smp_processor_id());
+ prom_halt();
+ }
+ sun4v_register_mondo_queues(cpu);
+ }
}
/* Only invoked on boot processor. */
kill_prom_timer();
memset(&ivector_table[0], 0, sizeof(ivector_table));
+ if (tlb_type == hypervisor)
+ sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
+
/* We need to clear any IRQ's pending in the soft interrupt
* registers, a spurious one could be left around from the
* PROM timer which we just disabled.
projects / firefly-linux-kernel-4.4.55.git / blobdiff