Merge branch 'x86/header-guards' into x86-v28-for-linus-phase1

[firefly-linux-kernel-4.4.55.git] / arch / sh / drivers / pci / pci-sh7780.h

diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index f02d2180a4bc2431b7f9a2a339231be47589aacb..97b2c98f05c473ae82a377d9b8b08e8abb77a70a 100644 (file)
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -14,8 +14,10 @@
 
 /* Platform Specific Values */
 #define SH7780_VENDOR_ID       0x1912
-#define SH7780_DEVICE_ID       0x0002
 #define SH7781_DEVICE_ID       0x0001
+#define SH7780_DEVICE_ID       0x0002
+#define SH7763_DEVICE_ID       0x0004
+#define SH7785_DEVICE_ID       0x0007
 
 /* SH7780 Control Registers */
 #define        SH7780_PCI_VCR0         0xFE000000
@@ -29,7 +31,7 @@
 #define SH7780_PCI_MEMORY_BASE 0xFD000000      /* Memory space base addr */
 #define SH7780_PCI_MEM_SIZE    0x01000000      /* Size of Memory window */
 
-#define SH7780_PCI_IO_BASE     0xFE400000      /* IO space base address */
+#define SH7780_PCI_IO_BASE     0xFE200000      /* IO space base address */
 #define SH7780_PCI_IO_SIZE     0x00400000      /* Size of IO window */
 
 #define SH7780_PCIREG_BASE     0xFE040000      /* PCI regs base address */
@@ -65,6 +67,22 @@
 #define SH7780_PCIPMCSR_BSE    0x046
 #define SH7780_PCICDD          0x047
 
+#define SH7780_PCICR           0x100           /* PCI Control Register */
+#define SH7780_PCILSR          0x104           /* PCI Local Space Register0 */
+#define SH7780_PCILSR1         0x108           /* PCI Local Space Register1 */
+#define SH7780_PCILAR0         0x10C           /* PCI Local Address Register1 */
+#define SH7780_PCILAR1         0x110           /* PCI Local Address Register1 */
+#define SH7780_PCIIR           0x114           /* PCI Interrupt Register */
+#define SH7780_PCIIMR          0x118           /* PCI Interrupt Mask Register */
+#define SH7780_PCIAIR          0x11C           /* Error Address Register */
+#define SH7780_PCICIR          0x120           /* Error Command/Data Register */
+#define SH7780_PCIAINT         0x130           /* Arbiter Interrupt Register */
+#define SH7780_PCIAINTM                0x134           /* Arbiter Int. Mask Register */
+#define SH7780_PCIBMIR         0x138           /* Error Bus Master Register */
+#define SH7780_PCIPAR          0x1C0           /* PIO Address Register */
+#define SH7780_PCIPINT         0x1CC           /* Power Mgmnt Int. Register */
+#define SH7780_PCIPINTM                0x1D0           /* Power Mgmnt Mask Register */
+
 #define SH7780_PCIMBR0         0x1E0
 #define SH7780_PCIMBMR0                0x1E4
 #define SH7780_PCIMBR2         0x1F0