Merge branch 'kvm-arm/vgic-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git...

[firefly-linux-kernel-4.4.55.git] / arch / mips / include / asm / mach-cavium-octeon / kernel-entry-init.h

diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index dedef7d2b01f579f9081a536e7540c54c353e154..1e7dbb192657fb454c6ef91fe9db9e2fd0f4f7e9 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -16,7 +16,7 @@
 #define CP0_PRID_OCTEON_PASS1 0x000d0000
 #define CP0_PRID_OCTEON_CN30XX 0x000d0200
 
-.macro  kernel_entry_setup
+.macro kernel_entry_setup
        # Registers set by bootloader:
        # (only 32 bits set by bootloader, all addresses are physical
        # addresses, and need to have the appropriate memory region set
@@ -28,12 +28,12 @@
        .set push
        .set arch=octeon
        # Read the cavium mem control register
-       dmfc0   v0, CP0_CVMMEMCTL_REG
+       dmfc0   v0, CP0_CVMMEMCTL_REG
        # Clear the lower 6 bits, the CVMSEG size
-       dins    v0, $0, 0, 6
-       ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
-       dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
-       dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register
+       dins    v0, $0, 0, 6
+       ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+       dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
+       dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register
 #ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
        # Disable unaligned load/store support but leave HW fixup enabled
        or  v0, v0, 0x5001
@@ -69,14 +69,14 @@ skip:
        and     v0, v0, v1
        ori     v0, v0, (6 << 7)
        # Write the cavium control register
-       dmtc0   v0, CP0_CVMCTL_REG
+       dmtc0   v0, CP0_CVMCTL_REG
        sync
        # Flush dcache after config change
-       cache   9, 0($0)
+       cache   9, 0($0)
        # Get my core id
-       rdhwr   v0, $0
+       rdhwr   v0, $0
        # Jump the master to kernel_entry
-       bne     a2, zero, octeon_main_processor
+       bne     a2, zero, octeon_main_processor
        nop
 
 #ifdef CONFIG_SMP
@@ -87,21 +87,21 @@ skip:
        #
 
        # This is the variable where the next core to boot os stored
-       PTR_LA  t0, octeon_processor_boot
+       PTR_LA  t0, octeon_processor_boot
 octeon_spin_wait_boot:
        # Get the core id of the next to be booted
-       LONG_L  t1, (t0)
+       LONG_L  t1, (t0)
        # Keep looping if it isn't me
        bne t1, v0, octeon_spin_wait_boot
        nop
        # Get my GP from the global variable
-       PTR_LA  t0, octeon_processor_gp
-       LONG_L  gp, (t0)
+       PTR_LA  t0, octeon_processor_gp
+       LONG_L  gp, (t0)
        # Get my SP from the global variable
-       PTR_LA  t0, octeon_processor_sp
-       LONG_L  sp, (t0)
+       PTR_LA  t0, octeon_processor_sp
+       LONG_L  sp, (t0)
        # Set the SP global variable to zero so the master knows we've started
-       LONG_S  zero, (t0)
+       LONG_S  zero, (t0)
 #ifdef __OCTEON__
        syncw
        syncw
@@ -130,7 +130,7 @@ octeon_main_processor:
 /*
  * Do SMP slave processor setup necessary before we can savely execute C code.
  */
-       .macro  smp_slave_setup
+       .macro  smp_slave_setup
        .endm
 
 #endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */