Merge tag 'v3.10.86' into linux-linaro-lsk-v3.10

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / include / asm / cputype.h

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index be9b5ca9a6c0228f5fced7925647c9dbb738b8bb..539bea61f129d9cc2aba9cb95a5a9acb9d406ce0 100644 (file)
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -16,31 +16,54 @@
 #ifndef __ASM_CPUTYPE_H
 #define __ASM_CPUTYPE_H
 
-#define ID_MIDR_EL1            "midr_el1"
-#define ID_MPIDR_EL1           "mpidr_el1"
-#define ID_CTR_EL0             "ctr_el0"
-
-#define ID_AA64PFR0_EL1                "id_aa64pfr0_el1"
-#define ID_AA64DFR0_EL1                "id_aa64dfr0_el1"
-#define ID_AA64AFR0_EL1                "id_aa64afr0_el1"
-#define ID_AA64ISAR0_EL1       "id_aa64isar0_el1"
-#define ID_AA64MMFR0_EL1       "id_aa64mmfr0_el1"
-
 #define INVALID_HWID           ULONG_MAX
 
 #define MPIDR_HWID_BITMASK     0xff00ffffff
 
+#define MPIDR_LEVEL_BITS_SHIFT 3
+#define MPIDR_LEVEL_BITS       (1 << MPIDR_LEVEL_BITS_SHIFT)
+#define MPIDR_LEVEL_MASK       ((1 << MPIDR_LEVEL_BITS) - 1)
+
+#define MPIDR_LEVEL_SHIFT(level) \
+       (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
+
+#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
+       ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
+
 #define read_cpuid(reg) ({                                             \
        u64 __val;                                                      \
-       asm("mrs        %0, " reg : "=r" (__val));                      \
+       asm("mrs        %0, " #reg : "=r" (__val));                     \
        __val;                                                          \
 })
 
+#define MIDR_REVISION_MASK     0xf
+#define MIDR_REVISION(midr)    ((midr) & MIDR_REVISION_MASK)
+#define MIDR_PARTNUM_SHIFT     4
+#define MIDR_PARTNUM_MASK      (0xfff << MIDR_PARTNUM_SHIFT)
+#define MIDR_PARTNUM(midr)     \
+       (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
+#define MIDR_ARCHITECTURE_SHIFT        16
+#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
+#define MIDR_ARCHITECTURE(midr)        \
+       (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
+#define MIDR_VARIANT_SHIFT     20
+#define MIDR_VARIANT_MASK      (0xf << MIDR_VARIANT_SHIFT)
+#define MIDR_VARIANT(midr)     \
+       (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
+#define MIDR_IMPLEMENTOR_SHIFT 24
+#define MIDR_IMPLEMENTOR_MASK  (0xff << MIDR_IMPLEMENTOR_SHIFT)
+#define MIDR_IMPLEMENTOR(midr) \
+       (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
+
 #define ARM_CPU_IMP_ARM                0x41
+#define ARM_CPU_IMP_APM                0x50
+
+#define ARM_CPU_PART_AEM_V8    0xD0F
+#define ARM_CPU_PART_FOUNDATION        0xD00
+#define ARM_CPU_PART_CORTEX_A57        0xD07
+#define ARM_CPU_PART_CORTEX_A53        0xD03
 
-#define ARM_CPU_PART_AEM_V8    0xD0F0
-#define ARM_CPU_PART_FOUNDATION        0xD000
-#define ARM_CPU_PART_CORTEX_A57        0xD070
+#define APM_CPU_PART_POTENZA   0x000
 
 #ifndef __ASSEMBLY__
 
@@ -51,27 +74,27 @@
  */
 static inline u32 __attribute_const__ read_cpuid_id(void)
 {
-       return read_cpuid(ID_MIDR_EL1);
+       return read_cpuid(MIDR_EL1);
 }
 
 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
 {
-       return read_cpuid(ID_MPIDR_EL1);
+       return read_cpuid(MPIDR_EL1);
 }
 
 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 {
-       return (read_cpuid_id() & 0xFF000000) >> 24;
+       return MIDR_IMPLEMENTOR(read_cpuid_id());
 }
 
 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 {
-       return (read_cpuid_id() & 0xFFF0);
+       return MIDR_PARTNUM(read_cpuid_id());
 }
 
 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
 {
-       return read_cpuid(ID_CTR_EL0);
+       return read_cpuid(CTR_EL0);
 }
 
 void cpuinfo_store_cpu(void);