opp00 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <925000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1025000>;
};
};
opp00 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <850000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <925000>;
};
};
status = "disabled";
};
+ rga: rga@ff680000 {
+ compatible = "rockchip,rk3399-rga";
+ reg = <0x0 0xff680000 0x0 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
+ clock-names = "aclk", "hclk", "sclk";
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
+ reset-names = "core", "axi", "ahb";
+ status = "disabled";
+ };
+
pmucru: pmu-clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <900000>;
};
- opp03 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <900000>;
- };
+
};
vopl: vop@ff8f0000 {