opp00 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <925000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1025000>;
};
};
opp00 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <800000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <850000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <925000>;
};
};
status = "disabled";
};
- usb2phy {
+ usb2phy: usb2phy {
compatible = "rockchip,rk3399-usb-phy";
rockchip,grf = <&grf>;
- vbus_drv-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "rockchip,dwc3";
clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
- <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
- <&cru ACLK_USB3_GRF>;
+ <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
"aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
- "aclk_usb3", "aclk_usb3_noc",
- "aclk_usb3_grf";
+ "aclk_usb3", "aclk_usb3_grf";
#address-cells = <2>;
#size-cells = <2>;
ranges;
compatible = "rockchip,dwc3";
clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
- <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
- <&cru ACLK_USB3_GRF>;
+ <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
"aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
- "aclk_usb3", "aclk_usb3_noc",
- "aclk_usb3_grf";
+ "aclk_usb3", "aclk_usb3_grf";
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
thermal-zones {
- #include "rk3368-thermal.dtsi"
+ cpu {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
+ temperature = <75000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <95000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ gpu_alert0: gpu_alert0 {
+ temperature = <75000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
+ temperature = <950000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
};
tsadc: tsadc@ff260000 {
status = "disabled";
};
+ rga: rga@ff680000 {
+ compatible = "rockchip,rk3399-rga";
+ reg = <0x0 0xff680000 0x0 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
+ clock-names = "aclk", "hclk", "sclk";
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
+ reset-names = "core", "axi", "ahb";
+ status = "disabled";
+ };
+
pmucru: pmu-clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
+ <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
+ <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
<&cru ARMCLKL>, <&cru ARMCLKB>,
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>,
<&cru PCLK_PERILP0>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
assigned-clock-rates =
+ <400000000>, <200000000>,
+ <400000000>, <200000000>,
<816000000>, <1008000000>,
<594000000>, <800000000>,
<1000000000>,
i2s0: i2s@ff880000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff880000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
dmas = <&dmac_bus 2>, <&dmac_bus 3>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff8a0000 0x0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
dmas = <&dmac_bus 4>, <&dmac_bus 5>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru ACLK_GPU>;
clock-names = "clk_mali";
+ #cooling-cells = <2>; /* min followed by max */
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
};
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <900000>;
};
- opp03 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <900000>;
+
+ };
+
+ vopl: vop@ff8f0000 {
+ compatible = "rockchip,rk3399-vop-lit";
+ reg = <0x0 0xff8f0000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
+ reset-names = "axi", "ahb", "dclk";
+ iommus = <&vopl_mmu>;
+ status = "disabled";
+
+ vopl_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vopl_out_mipi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
+
+ vopl_out_edp: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&edp_in_vopl>;
+ };
};
};
+ vopl_mmu: iommu@ff8f3f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff8f3f00 0x0 0x100>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vopl_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vopb: vop@ff900000 {
+ compatible = "rockchip,rk3399-vop-big";
+ reg = <0x0 0xff900000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
+ reset-names = "axi", "ahb", "dclk";
+ iommus = <&vopb_mmu>;
+ status = "disabled";
+
+ vopb_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vopb_out_edp: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&edp_in_vopb>;
+ };
+
+ vopb_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
+ };
+ };
+
+ vopb_mmu: iommu@ff903f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff903f00 0x0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vopb_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_dsi: mipi@ff960000 {
+ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x0 0xff960000 0x0 0x8000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+ <&cru SCLK_DPHY_TX0_CFG>;
+ clock-names = "ref", "pclk", "phy_cfg";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
+ edp: edp@ff970000 {
+ compatible = "rockchip,rk3399-edp";
+ reg = <0x0 0xff970000 0x0 0x8000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ resets = <&cru SRST_P_EDP_CTRL>;
+ reset-names = "dp";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_edp>;
+ };
+
+ edp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_edp>;
+ };
+ };
+ };
+ };
+
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vopl_out>, <&vopb_out>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3399-pinctrl";
rockchip,grf = <&grf>;
drive-strength = <12>;
};
+ pcfg_pull_none_13ma: pcfg-pull-none-13ma {
+ bias-disable;
+ drive-strength = <13>;
+ };
+
emmc {
emmc_pwr: emmc-pwr {
rockchip,pins =
rgmii_pins: rgmii-pins {
rockchip,pins =
/* mac_txclk */
- <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_rxclk */
<3 14 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdio */
<3 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
- <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_clk */
<3 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxdv */
/* mac_rxd0 */
<3 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
- <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd0 */
- <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_rxd3 */
<3 3 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd2 */
<3 2 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd3 */
- <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd2 */
- <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
+ <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
};
rmii_pins: rmii-pins {
/* mac_mdio */
<3 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
- <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_clk */
<3 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxer */
/* mac_rxd0 */
<3 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
- <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd0 */
- <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
+ <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
};
};
};
};
- pmic {
- pmic_int_l: pmic-int-l {
+ edp {
+ edp_hpd: edp-hpd {
rockchip,pins =
- <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+ <4 23 RK_FUNC_2 &pcfg_pull_none>;
};
};
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff