#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/display/rk_fb.h>
+#include <dt-bindings/display/mipi_dsi.h>
+#include <dt-bindings/power/rk3368-power.h>
+#include <dt-bindings/soc/rockchip_boot-mode.h>
/ {
compatible = "rockchip,rk3368";
reg = <0x0 0x0>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ clocks = <&cru ARMCLKL>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_l1: cpu@1 {
reg = <0x0 0x1>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ clocks = <&cru ARMCLKL>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_l2: cpu@2 {
reg = <0x0 0x2>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ clocks = <&cru ARMCLKL>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_l3: cpu@3 {
reg = <0x0 0x3>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ clocks = <&cru ARMCLKL>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b0: cpu@100 {
reg = <0x0 0x100>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ clocks = <&cru ARMCLKB>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_b1: cpu@101 {
reg = <0x0 0x101>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ clocks = <&cru ARMCLKB>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_b2: cpu@102 {
reg = <0x0 0x102>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ clocks = <&cru ARMCLKB>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_b3: cpu@103 {
reg = <0x0 0x103>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ clocks = <&cru ARMCLKB>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+ };
+
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <1200000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1200000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <1200000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000>;
};
};
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC_PERI>;
clock-names = "apb_pclk";
+ arm,pl330-broken-no-flushp;
+ peripherals-req-type-burst;
};
dmac_bus: dma-controller@ff600000 {
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC_BUS>;
clock-names = "apb_pclk";
+ arm,pl330-broken-no-flushp;
+ peripherals-req-type-burst;
};
};
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
status = "disabled";
};
- i2c1: i2c@ff140000 {
+ i2c0: i2c@ff650000 {
+ compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+ reg = <0x0 0xff650000 0x0 0x1000>;
+ clocks = <&cru PCLK_I2C0>;
+ clock-names = "i2c";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ff140000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff140000 0x0 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
- clocks = <&cru PCLK_I2C1>;
+ clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
+ pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
status = "disabled";
};
+ nandc0: nandc@ff400000 {
+ compatible = "rockchip,rk-nandc";
+ reg = <0x0 0xff400000 0x0 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ nandc_id = <0>;
+ clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
+ clock-names = "clk_nandc", "hclk_nandc";
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@ff500000 {
compatible = "generic-ehci";
reg = <0x0 0xff500000 0x0 0x100>;
reg = <0x0 0xff610000 0x0 0x400>;
};
- i2c0: i2c@ff650000 {
- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
- reg = <0x0 0xff650000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C0>;
- clock-names = "i2c";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@ff660000 {
+ i2c1: i2c@ff660000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff660000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
- clocks = <&cru PCLK_I2C2>;
+ clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
+ pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
};
pmu: power-management@ff730000 {
- compatible = "rockchip,rk3368-pmu", "syscon";
+ compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff730000 0x0 0x1000>;
+
+ power: power-controller {
+ status = "disabled";
+ compatible = "rockchip,rk3368-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * Note: Although SCLK_* are the working clocks
+ * of device without including on the NOC, needed for
+ * synchronous reset.
+ *
+ * The clocks on the which NOC:
+ * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+ * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+ * ACLK_RGA is on ACLK_RGA_NIU.
+ * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+ *
+ * Which clock are device clocks:
+ * clocks devices
+ * *_IEP IEP:Image Enhancement Processor
+ * *_ISP ISP:Image Signal Processing
+ * *_VIP VIP:Video Input Processor
+ * *_VOP* VOP:Visual Output Processor
+ * *_RGA RGA
+ * *_EDP* EDP
+ * *_DPHY* LVDS
+ * *_HDMI HDMI
+ * *_MIPI_* MIPI
+ */
+ pd_vio {
+ reg = <RK3368_PD_VIO>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru ACLK_ISP>,
+ <&cru ACLK_VIP>,
+ <&cru ACLK_RGA>,
+ <&cru ACLK_VOP>,
+ <&cru ACLK_VOP_IEP>,
+ <&cru DCLK_VOP>,
+ <&cru HCLK_IEP>,
+ <&cru HCLK_ISP>,
+ <&cru HCLK_RGA>,
+ <&cru HCLK_VIP>,
+ <&cru HCLK_VOP>,
+ <&cru HCLK_VIO_HDCPMMU>,
+ <&cru PCLK_EDP_CTRL>,
+ <&cru PCLK_HDMI_CTRL>,
+ <&cru PCLK_HDCP>,
+ <&cru PCLK_ISP>,
+ <&cru PCLK_VIP>,
+ <&cru PCLK_DPHYRX>,
+ <&cru PCLK_DPHYTX0>,
+ <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_MIPI_DSI0>,
+ <&cru SCLK_VOP0_PWM>,
+ <&cru SCLK_EDP_24M>,
+ <&cru SCLK_EDP>,
+ <&cru SCLK_HDCP>,
+ <&cru SCLK_ISP>,
+ <&cru SCLK_RGA>,
+ <&cru SCLK_HDMI_CEC>,
+ <&cru SCLK_HDMI_HDCP>;
+ };
+ /*
+ * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+ * (video endecoder & decoder) clocks that on the
+ * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+ */
+ pd_video {
+ reg = <RK3368_PD_VIDEO>;
+ clocks = <&cru ACLK_VIDEO>,
+ <&cru HCLK_VIDEO>,
+ <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>;
+ };
+ /*
+ * Note: ACLK_GPU is the GPU clock,
+ * and on the ACLK_GPU_NIU (NOC).
+ */
+ pd_gpu_1 {
+ reg = <RK3368_PD_GPU_1>;
+ clocks = <&cru ACLK_GPU_CFG>,
+ <&cru ACLK_GPU_MEM>,
+ <&cru SCLK_GPU_CORE>;
+ };
+ };
};
pmugrf: syscon@ff738000 {
- compatible = "rockchip,rk3368-pmugrf", "syscon";
+ compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x200>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_LOADER>;
+
+ };
};
cru: clock-controller@ff760000 {
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+ assigned-clocks =
+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ <&cru PLL_NPLL>,
+ <&cru ACLK_BUS>, <&cru ACLK_PERI>,
+ <&cru HCLK_BUS>, <&cru HCLK_PERI>,
+ <&cru PCLK_BUS>, <&cru PCLK_PERI>;
+ assigned-clock-rates =
+ <576000000>, <400000000>,
+ <1188000000>,
+ <300000000>, <300000000>,
+ <150000000>, <150000000>,
+ <75000000>, <75000000>;
};
grf: syscon@ff770000 {
#address-cells = <0>;
reg = <0x0 0xffb71000 0x0 0x1000>,
- <0x0 0xffb72000 0x0 0x1000>,
+ <0x0 0xffb72000 0x0 0x2000>,
<0x0 0xffb74000 0x0 0x2000>,
<0x0 0xffb76000 0x0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ gpu: rogue-g6110@ffa30000 {
+ compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
+ reg = <0x0 0xffa30000 0x0 0x10000>;
+ clocks =
+ <&cru SCLK_GPU_CORE>,
+ <&cru ACLK_GPU_MEM>,
+ <&cru ACLK_GPU_CFG>;
+ clock-names =
+ "sclk_gpu_core",
+ "aclk_gpu_mem",
+ "aclk_gpu_cfg";
+ operating-points = <
+ /* KHz uV */
+ 200000 1100000
+ 288000 1100000
+ 400000 1150000
+ 576000 1200000
+ >;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rogue-g6110-irq";
+ };
+
i2s_2ch: i2s-2ch@ff890000 {
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff898000 0x0 0x1000>;
+ reg = <0x0 0xff890000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <2>;
- #size-cells = <0>;
dmas = <&dmac_bus 6>, <&dmac_bus 7>;
dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
status = "disabled";
};
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff898000 0x0 0x1000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_bus>;
status = "disabled";
};
+ isp: isp@ff910000 {
+ compatible = "rockchip,rk3368-isp", "rockchip,isp";
+ reg = <0x0 0xff910000 0x0 0x10000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ /*power-domains = <&power PD_VIO>;*/
+ clocks =
+ <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
+ <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
+ <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
+ clock-names =
+ "aclk_isp", "hclk_isp", "clk_isp",
+ "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
+ "clk_cif_pll", "hclk_mipiphy1",
+ "pclk_dphyrx", "clk_vio0_noc";
+ pinctrl-names =
+ "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
+ "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
+ "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+ "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
+ pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
+ pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
+ pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
+ pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
+ pinctrl-6 = <&cif_clkout>;
+ pinctrl-7 = <&cif_clkout &isp_prelight>;
+ pinctrl-8 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-9 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
+ rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu_enable = <1>;
+ status = "disabled";
+ };
+
+ rga: rga@ff920000 {
+ compatible = "rockchip,rga2";
+ dev_mode = <1>;
+ reg = <0x0 0xff920000 0x0 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk_rga", "hclk_rga", "clk_rga";
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3368-pinctrl";
rockchip,grf = <&grf>;
};
};
+ hdmi_i2c {
+ hdmii2c_xfer: hdmii2c-xfer {
+ rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
+ <3 27 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi_pin {
+ hdmi_cec: hdmi-cec {
+ rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
<3 27 RK_FUNC_2 &pcfg_pull_none>;
};
+ i2c5_gpio: i2c5-gpio {
+ rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
i2s {
<0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
};
};
+
+ isp {
+ cif_clkout: cif-clkout {
+ rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
+ };
+
+ isp_dvp_d2d9: isp-dvp-d2d9 {
+ rockchip,pins =
+ <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
+ <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
+ <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
+ <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
+ <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
+ <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
+ <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
+ <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
+ <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
+ <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
+ <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
+ <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
+ };
+
+ isp_dvp_d0d1: isp-dvp-d0d1 {
+ rockchip,pins =
+ <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
+ <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
+ };
+
+ isp_dvp_d10d11:isp_d10d11 {
+ rockchip,pins =
+ <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
+ <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
+ };
+
+ isp_dvp_d0d7: isp-dvp-d0d7 {
+ rockchip,pins =
+ <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
+ <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
+ <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
+ <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
+ <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
+ <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
+ <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
+ <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
+ };
+
+ isp_dvp_d4d11: isp-dvp-d4d11 {
+ rockchip,pins =
+ <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
+ <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
+ <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
+ <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
+ <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
+ <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
+ <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
+ <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
+ };
+
+ isp_shutter: isp-shutter {
+ rockchip,pins =
+ <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
+ <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
+ };
+
+ isp_flash_trigger: isp-flash-trigger {
+ rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
+ };
+
+ isp_prelight: isp-prelight {
+ rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
+ };
+
+ isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
+ rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
+ };
+ };
};
fb: fb {
status = "disabled";
};
+ hdmi: hdmi@ff980000 {
+ compatible = "rockchip,rk3368-hdmi";
+ reg = <0x0 0xff980000 0x0 0x20000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI_CTRL>,
+ <&cru SCLK_HDMI_HDCP>,
+ <&cru SCLK_HDMI_CEC>;
+ clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
+ /*power-domains = <&power PD_VIO>;*/
+ resets = <&cru SRST_HDMI>;
+ reset-names = "hdmi";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
+ pinctrl-1 = <&i2c5_gpio>;
+ status = "disabled";
+ };
+
iep_mmu: iep-mmu {
dbgname = "iep";
compatible = "rockchip,iep_mmu";
projects / firefly-linux-kernel-4.4.55.git / blobdiff