arm64: dts: rockchip: add allocator type inside vpu & rkvdec for rk3399-android

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3368.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 42e7a69b1882b648fa1aa62d4c3cc37906c754e7..fd69e074c0252adb37b35bb0b96d74246307ef56 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -46,7 +46,9 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/display/rk_fb.h>
+#include <dt-bindings/display/mipi_dsi.h>
 #include <dt-bindings/power/rk3368-power.h>
+#include <dt-bindings/soc/rockchip_boot-mode.h>
 
 / {
        compatible = "rockchip,rk3368";
@@ -136,6 +138,7 @@
                        reg = <0x0 0x1>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLKL>;
                        operating-points-v2 = <&cluster1_opp>;
                };
 
@@ -145,6 +148,7 @@
                        reg = <0x0 0x2>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLKL>;
                        operating-points-v2 = <&cluster1_opp>;
                };
 
@@ -154,6 +158,7 @@
                        reg = <0x0 0x3>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLKL>;
                        operating-points-v2 = <&cluster1_opp>;
                };
 
@@ -173,6 +178,7 @@
                        reg = <0x0 0x101>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLKB>;
                        operating-points-v2 = <&cluster0_opp>;
                };
 
@@ -182,6 +188,7 @@
                        reg = <0x0 0x102>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLKB>;
                        operating-points-v2 = <&cluster0_opp>;
                };
 
@@ -191,6 +198,7 @@
                        reg = <0x0 0x103>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLKB>;
                        operating-points-v2 = <&cluster0_opp>;
                };
        };
@@ -199,25 +207,25 @@
                compatible = "operating-points-v2";
                opp-shared;
 
-               opp00 {
+               opp@408000000 {
                        opp-hz = /bits/ 64 <408000000>;
                        opp-microvolt = <1200000>;
                        clock-latency-ns = <40000>;
                        opp-suspend;
                };
-               opp01 {
+               opp@600000000 {
                        opp-hz = /bits/ 64 <600000000>;
                        opp-microvolt = <1200000>;
                };
-               opp02 {
+               opp@816000000 {
                        opp-hz = /bits/ 64 <816000000>;
                        opp-microvolt = <1200000>;
                };
-               opp03 {
+               opp@1008000000 {
                        opp-hz = /bits/ 64 <1008000000>;
                        opp-microvolt = <1200000>;
                };
-               opp04 {
+               opp@1200000000 {
                        opp-hz = /bits/ 64 <1200000000>;
                        opp-microvolt = <1200000>;
                };
@@ -227,21 +235,21 @@
                compatible = "operating-points-v2";
                opp-shared;
 
-               opp00 {
+               opp@408000000 {
                        opp-hz = /bits/ 64 <408000000>;
                        opp-microvolt = <1200000>;
                        clock-latency-ns = <40000>;
                        opp-suspend;
                };
-               opp01 {
+               opp@600000000 {
                        opp-hz = /bits/ 64 <600000000>;
                        opp-microvolt = <1200000>;
                };
-               opp02 {
+               opp@816000000 {
                        opp-hz = /bits/ 64 <816000000>;
                        opp-microvolt = <1200000>;
                };
-               opp03 {
+               opp@1008000000 {
                        opp-hz = /bits/ 64 <1008000000>;
                        opp-microvolt = <1200000>;
                };
@@ -276,6 +284,8 @@
                        #dma-cells = <1>;
                        clocks = <&cru ACLK_DMAC_PERI>;
                        clock-names = "apb_pclk";
+                       arm,pl330-broken-no-flushp;
+                       peripherals-req-type-burst;
                };
 
                dmac_bus: dma-controller@ff600000 {
@@ -286,6 +296,8 @@
                        #dma-cells = <1>;
                        clocks = <&cru ACLK_DMAC_BUS>;
                        clock-names = "apb_pclk";
+                       arm,pl330-broken-no-flushp;
+                       peripherals-req-type-burst;
                };
        };
 
@@ -354,6 +366,8 @@
                #io-channel-cells = <1>;
                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
                clock-names = "saradc", "apb_pclk";
+               resets = <&cru SRST_SARADC>;
+               reset-names = "saradc-apb";
                status = "disabled";
        };
 
@@ -726,8 +740,18 @@
        };
 
        pmugrf: syscon@ff738000 {
-               compatible = "rockchip,rk3368-pmugrf", "syscon";
+               compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
                reg = <0x0 0xff738000 0x0 0x1000>;
+
+               reboot-mode {
+                       compatible = "syscon-reboot-mode";
+                       offset = <0x200>;
+                       mode-normal = <BOOT_NORMAL>;
+                       mode-recovery = <BOOT_RECOVERY>;
+                       mode-bootloader = <BOOT_FASTBOOT>;
+                       mode-loader = <BOOT_LOADER>;
+
+               };
        };
 
        cru: clock-controller@ff760000 {
@@ -770,7 +794,7 @@
                #address-cells = <0>;
 
                reg = <0x0 0xffb71000 0x0 0x1000>,
-                     <0x0 0xffb72000 0x0 0x1000>,
+                     <0x0 0xffb72000 0x0 0x2000>,
                      <0x0 0xffb74000 0x0 0x2000>,
                      <0x0 0xffb76000 0x0 0x2000>;
                interrupts = <GIC_PPI 9
@@ -805,8 +829,8 @@
                interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                dmas = <&dmac_bus 6>, <&dmac_bus 7>;
                dma-names = "tx", "rx";
-               clock-names = "i2s_hclk", "i2s_clk";
-               clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
+               clock-names = "i2s_clk", "i2s_hclk";
+               clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
                status = "disabled";
        };
 
@@ -816,8 +840,8 @@
                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                dmas = <&dmac_bus 0>, <&dmac_bus 1>;
                dma-names = "tx", "rx";
-               clock-names = "i2s_hclk", "i2s_clk";
-               clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
+               clock-names = "i2s_clk", "i2s_hclk";
+               clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2s_8ch_bus>;
                status = "disabled";