#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/display/rk_fb.h>
/ {
compatible = "rockchip,rk3368";
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
+ lcdc = &lcdc;
};
cpus {
<&cpu_b2>, <&cpu_b3>;
};
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dmac_peri: dma-controller@ff250000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff250000 0x0 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&cru ACLK_DMAC_PERI>;
+ clock-names = "apb_pclk";
+ };
+
+ dmac_bus: dma-controller@ff600000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff600000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&cru ACLK_DMAC_BUS>;
+ clock-names = "apb_pclk";
+ };
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
#clock-cells = <0>;
};
- sdmmc: dwmmc@ff0c0000 {
+ sdmmc: rksdmmc@ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
status = "disabled";
};
- emmc: dwmmc@ff0f0000 {
+ emmc: rksdmmc@ff0f0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0f0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
status = "disabled";
};
- i2c1: i2c@ff140000 {
+ i2c2: i2c@ff140000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff140000 0x0 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
- clocks = <&cru PCLK_I2C1>;
+ clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
+ pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
status = "disabled";
};
+ ddrpctl: syscon@ff610000 {
+ compatible = "rockchip,rk3368-ddrpctl", "syscon";
+ reg = <0x0 0xff610000 0x0 0x400>;
+ };
+
i2c0: i2c@ff650000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff650000 0x0 0x1000>;
status = "disabled";
};
- i2c2: i2c@ff660000 {
+ i2c1: i2c@ff660000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff660000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
- clocks = <&cru PCLK_I2C2>;
+ clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
+ pinctrl-0 = <&i2c1_xfer>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@ff680000 {
+ compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+ reg = <0x0 0xff680000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ clocks = <&cru PCLK_PWM1>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm1: pwm@ff680010 {
+ compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+ reg = <0x0 0xff680010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ clocks = <&cru PCLK_PWM1>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm2: pwm@ff680020 {
+ compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+ reg = <0x0 0xff680020 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&cru PCLK_PWM1>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm3: pwm@ff680030 {
+ compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+ reg = <0x0 0xff680030 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ clocks = <&cru PCLK_PWM1>;
+ clock-names = "pwm";
status = "disabled";
};
status = "disabled";
};
+ pmu: power-management@ff730000 {
+ compatible = "rockchip,rk3368-pmu", "syscon";
+ reg = <0x0 0xff730000 0x0 0x1000>;
+ };
+
pmugrf: syscon@ff738000 {
compatible = "rockchip,rk3368-pmugrf", "syscon";
reg = <0x0 0xff738000 0x0 0x1000>;
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ gpu: rogue-g6110@ffa30000 {
+ compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
+ reg = <0x0 0xffa30000 0x0 0x10000>;
+ clocks =
+ <&cru SCLK_GPU_CORE>,
+ <&cru ACLK_GPU_MEM>,
+ <&cru ACLK_GPU_CFG>;
+ clock-names =
+ "clk_gpu",
+ "aclk_gpu_mem",
+ "aclk_gpu_cfg";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rogue-g6110-irq";
+ };
+
+ i2s_2ch: i2s-2ch@ff890000 {
+ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff898000 0x0 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ dmas = <&dmac_bus 6>, <&dmac_bus 7>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
+ status = "disabled";
+ };
+
+ i2s_8ch: i2s-8ch@ff898000 {
+ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff898000 0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_8ch_bus>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3368-pinctrl";
rockchip,grf = <&grf>;
};
};
+ i2s {
+ i2s_8ch_bus: i2s-8ch-bus {
+ rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
+ <2 13 RK_FUNC_1 &pcfg_pull_none>,
+ <2 14 RK_FUNC_1 &pcfg_pull_none>,
+ <2 15 RK_FUNC_1 &pcfg_pull_none>,
+ <2 16 RK_FUNC_1 &pcfg_pull_none>,
+ <2 17 RK_FUNC_1 &pcfg_pull_none>,
+ <2 18 RK_FUNC_1 &pcfg_pull_none>,
+ <2 19 RK_FUNC_1 &pcfg_pull_none>,
+ <2 20 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
sdio0 {
sdio0_bus1: sdio0-bus1 {
rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
};
};
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ vop_pwm_pin: vop-pwm {
+ rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
+ lcdc {
+ lcdc_lcdc: lcdc-lcdc {
+ rockchip,pins =
+ <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
+ <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
+ <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
+ <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
+ <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
+ <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
+ <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
+ <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
+ <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
+ <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
+ <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
+ <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
+ <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
+ <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
+ <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
+ <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
+ <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
+ <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
+ };
+
+ lcdc_gpio: lcdc-gpio {
+ rockchip,pins =
+ <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
+ <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
+ <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
+ <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
+ <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
+ <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
+ <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
+ <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
+ <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
+ <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
+ <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
+ <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
+ <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
+ <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
+ <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
+ <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
+ <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
+ <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
+ };
+ };
+ };
+
+ fb: fb {
+ compatible = "rockchip,rk-fb";
+ rockchip,disp-mode = <NO_DUAL>;
+ status = "disabled";
+ };
+
+ rk_screen: screen {
+ compatible = "rockchip,screen";
+ status = "disabled";
+ };
+
+ lcdc: lcdc@ff930000 {
+ compatible = "rockchip,rk3368-lcdc";
+ rockchip,grf = <&grf>;
+ rockchip,pmugrf = <&pmugrf>;
+ rockchip,cru = <&cru>;
+ rockchip,prop = <PRMRY>;
+ rockchip,pwr18 = <0>;
+ rockchip,iommu-enabled = <1>;
+ reg = <0x0 0xff930000 0x0 0x10000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
+ /*power-domains = <&power PD_VIO>;*/
+ resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+ };
+
+ mipi: mipi@ff960000 {
+ compatible = "rockchip,rk3368-dsi";
+ rockchip,prop = <0>;
+ reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
+ reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
+ /*power-domains = <&power PD_VIO>;*/
+ status = "disabled";
+ };
+
+ lvds: lvds@ff968000 {
+ compatible = "rockchip,rk3368-lvds";
+ rockchip,grf = <&grf>;
+ reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
+ reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
+ clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "pclk_lvds", "pclk_lvds_ctl";
+ /*power-domains = <&power PD_VIO>;*/
+ status = "disabled";
+ };
+
+ edp: edp@ff970000 {
+ compatible = "rockchip,rk32-edp";
+ reg = <0x0 0xff970000 0x0 0x4000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+ /*power-domains = <&power PD_VIO>;*/
+ resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
+ reset-names = "edp_24m", "edp_apb";
+ status = "disabled";
+ };
+
+ iep_mmu: iep-mmu {
+ dbgname = "iep";
+ compatible = "rockchip,iep_mmu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ status = "disabled";
+ };
+
+ vip_mmu: vip-mmu {
+ dbgname = "vip";
+ compatible = "rockchip,vip_mmu";
+ reg = <0x0 0xff950800 0x0 0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vip_mmu";
+ status = "disabled";
+ };
+
+ vopb_mmu: vopb-mmu {
+ dbgname = "vop";
+ compatible = "rockchip,vopb_mmu";
+ reg = <0x0 0xff930300 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ status = "disabled";
+ };
+
+ isp_mmu: isp-mmu {
+ dbgname = "isp_mmu";
+ compatible = "rockchip,isp_mmu";
+ reg = <0x0 0xff914000 0x0 0x100>,
+ <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ status = "disabled";
+ };
+
+ hdcp_mmu: hdcp-mmu {
+ dbgname = "hdcp_mmu";
+ compatible = "rockchip,hdcp_mmu";
+ reg = <0x0 0xff940000 0x0 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hdcp_mmu";
+ status = "disabled";
+ };
+
+ hevc_mmu: hevc-mmu {
+ dbgname = "hevc";
+ compatible = "rockchip,hevc_mmu";
+ reg = <0x0 0xff9a0440 0x0 0x40>,
+ <0x0 0xff9a0480 0x0 0x40>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ status = "disabled";
+ };
+
+ vpu_mmu: vpu-mmu {
+ dbgname = "vpu";
+ compatible = "rockchip,vpu_mmu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu_mmu", "vdpu_mmu";
+ status = "disabled";
};
};