ARM64: dts: rockchip: rk3366: add usb2.0 phy node
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3366.dtsi
index 484931c6aa887806757b9c479ab3fcd9ac2e4800..cd63084a1663bf804a4c027a9256106b97385b9b 100644 (file)
                status = "disabled";
        };
 
+       usbphy: phy {
+               compatible = "rockchip,rk336x-usb-phy";
+               rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               usbphy0: usb-phy0 {
+                       #phy-cells = <0>;
+                       #clock-cells = <0>;
+                       reg = <0x700>;
+               };
+
+               usbphy1: usb-phy1 {
+                       #phy-cells = <0>;
+                       #clock-cells = <0>;
+                       reg = <0x728>;
+               };
+       };
+
+       usb_host0_echi: usb@ff480000 {
+               compatible = "generic-ehci";
+               reg = <0x0 0xff480000 0x0 0x20000>;
+               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
+               clock-names = "sclk_otgphy0", "hclk_host0";
+               phys = <&usbphy1>;
+               phy-names = "usb";
+               status = "disabled";
+       };
+
+       usb_host0_ohci: usb@ff4a0000 {
+               compatible = "generic-ohci";
+               reg = <0x0 0xff4a0000 0x0 0x20000>;
+               interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
+               clock-names = "sclk_otgphy0", "hclk_host0";
+               status = "disabled";
+       };
+
        usb_otg: usb@ff4c0000 {
                compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
                             "snps,dwc2";
                assigned-clock-rates =
                        <750000000>, <576000000>,
                        <594000000>, <594000000>,
-                       <480000000>, <520000000>,
+                       <960000000>, <520000000>,
                        <375000000>, <288000000>,
                        <100000000>, <100000000>;
        };
                reg = <0x0 0xff770000 0x0 0x1000>;
        };
 
+       wdt: watchdog@ff800000 {
+               compatible = "snps,dw-wdt";
+               reg = <0x0 0xff800000 0x0 0x100>;
+               clocks = <&cru PCLK_WDT>;
+               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       spdif: spdif@ff880000 {
+               compatible = "rockchip,rk3366-spdif";
+               reg = <0x0 0xff880000 0x0 0x1000>;
+               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+               dmas = <&dmac_bus 3>;
+               dma-names = "tx";
+               clock-names = "hclk", "mclk";
+               clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spdif_bus>;
+               status = "disabled";
+       };
+
        i2s_2ch: i2s-2ch@ff890000 {
                compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
                reg = <0x0 0xff890000 0x0 0x1000>;
                status = "disabled";
        };
 
+       iep: iep@ff900000 {
+               compatible = "rockchip,iep";
+               iommu_enabled = <1>;
+               reg = <0x0 0xff900000 0x0 0x800>;
+               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+               clock-names = "aclk_iep", "hclk_iep";
+               version = <2>;
+               status = "disabled";
+       };
+
        rga: rga@ff920000 {
                compatible = "rockchip,rga2";
                dev_mode = <1>;
                status = "disabled";
        };
 
+       iep_mmu: iep-mmu {
+               dbgname = "iep";
+               compatible = "rockchip,iep_mmu";
+               reg = <0x0 0xff900800 0x0 0x100>;
+               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "iep_mmu";
+               status = "disabled";
+       };
+
+       vpu_mmu: vpu_mmu {
+               dbgname = "vpu";
+               compatible = "rockchip,vpu_mmu";
+               reg = <0x0 0xff9a0800 0x0 0x100>;
+               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vpu_mmu";
+               status = "disabled";
+       };
+
+       vdec_mmu: vdec_mmu {
+               dbgname = "vdec";
+               compatible = "rockchip,vdec_mmu";
+               reg = <0x0 0xff9b0480 0x0 0x40>,
+                     <0x0 0xff9b04c0 0x0 0x40>;
+               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vdec_mmu";
+               status = "disabled";
+       };
+
        dsihost0: mipi@ff960000 {
                compatible = "rockchip,rk3368-dsi";
                rockchip,prop = <0>;
                status = "disabled";
        };
 
+       vpu: vpu_service@ff9a0000 {
+               compatible = "rockchip,vpu_service";
+               rockchip,grf = <&grf>;
+               iommu_enabled = <1>;
+               reg = <0x0 0xff9a0000 0x0 0x800>;
+               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "irq_dec", "irq_enc";
+               clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+               clock-names = "aclk_vcodec", "hclk_vcodec";
+               resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
+               reset-names = "video_h", "video_a";
+               name = "vpu_service";
+               dev_mode = <0>;
+               status = "disabled";
+       };
+
+       rkvdec: rkvdec@ff9b0000 {
+               compatible = "rockchip,rkvdec";
+               rockchip,grf = <&grf>;
+               iommu_enabled = <1>;
+               reg = <0x0 0xff9b0000 0x0 0x400>;
+               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "irq_dec";
+               clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
+               clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
+               resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
+               reset-names = "video_h", "video_a";
+               dev_mode = <2>;
+               name = "rkvdec";
+               status = "disabled";
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3366-pinctrl";
                rockchip,grf = <&grf>;
                                        <5 15 RK_FUNC_2 &pcfg_pull_none>,
                                        <5 16 RK_FUNC_2 &pcfg_pull_none>;
                        };
+
+                       i2c2_gpio: i2c2-gpio {
+                               rockchip,pins =
+                                       <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
+                                       <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
+                       };
                };
 
                i2c3 {
                                        <5 8 RK_FUNC_1 &pcfg_pull_none>,
                                        <5 9 RK_FUNC_1 &pcfg_pull_none>;
                        };
+
+                       i2c4_gpio: i2c4-gpio {
+                               rockchip,pins =
+                                       <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
+                                       <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
+                       };
                };
 
                i2c5 {
                        };
                };
 
+               spdif {
+                       spdif_bus: spdif-bus {
+                               rockchip,pins =
+                                       <5 19 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
                spi0 {
                        spi0_clk: spi0-clk {
                                rockchip,pins =
                        };
                };
        };
+
+       gpu: gpu@ffa30000 {
+               compatible = "arm,malit764",
+                            "arm,malit76x",
+                            "arm,malit7xx",
+                            "arm,mali-midgard";
+
+               reg = <0x0 0xffa30000 0 0x10000>;
+
+               interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "GPU", "MMU", "JOB";
+
+               clocks = <&cru ACLK_GPU>;
+               clock-names = "clk_mali";
+               operating-points-v2 = <&gpu_opp_table>;
+               status = "disabled";
+       };
+
+       gpu_opp_table: gpu_opp_table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp00 {
+                       opp-hz = /bits/ 64 <96000000>;
+                       opp-microvolt = <1150000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <192000000>;
+                       opp-microvolt = <1150000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <288000000>;
+                       opp-microvolt = <1150000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <375000000>;
+                       opp-microvolt = <1150000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <480000000>;
+                       opp-microvolt = <1150000>;
+               };
+       };
 };