#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/display/rk_fb.h>
#include <dt-bindings/power/rk3366-power.h>
+#include <dt-bindings/soc/rockchip_boot-mode.h>
/ {
compatible = "rockchip,rk3366";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1075000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1175000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1250000>;
};
};
timer {
compatible = "arm,armv8-timer";
- interrupts = <
- GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
};
xin24m: xin24m {
status = "disabled";
};
+ scr: rkscr@ff1d0000 {
+ compatible = "rockchip-scr";
+ reg = <0x0 0xff1d0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
+ clocks = <&cru PCLK_SIM>;
+ clock-names = "g_pclk_sim_card";
+ status = "disabled";
+ };
+
sdmmc: rksdmmc@ff400000 {
compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
- <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
+ <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
clock-names = "stmmaceth", "mac_clk_rx",
status = "disabled";
};
+ usbphy: phy {
+ compatible = "rockchip,rk336x-usb-phy";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphy0: usb-phy0 {
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ reg = <0x700>;
+ };
+
+ usbphy1: usb-phy1 {
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ reg = <0x728>;
+ };
+ };
+
+ usb_host0_echi: usb@ff480000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff480000 0x0 0x20000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
+ clock-names = "sclk_otgphy0", "hclk_host0";
+ phys = <&usbphy1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff4a0000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff4a0000 0x0 0x20000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
+ clock-names = "sclk_otgphy0", "hclk_host0";
+ status = "disabled";
+ };
+
usb_otg: usb@ff4c0000 {
compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
"snps,dwc2";
};
pmugrf: syscon@ff738000 {
- compatible = "rockchip,rk3366-pmugrf", "syscon";
+ compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x200>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-fastboot = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_LOADER>;
+ };
};
amba {
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
+ <&cru SCLK_32K>,
+ <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
<&cru PLL_CPLL>, <&cru PLL_GPLL>,
<&cru PLL_NPLL>, <&cru PLL_MPLL>,
<&cru PLL_WPLL>, <&cru PLL_BPLL>,
<&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
- <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
+ <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
+ <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
+ <&cru ACLK_PERI1>;
assigned-clock-rates =
+ <0>,
+ <0>, <0>,
<750000000>, <576000000>,
<594000000>, <594000000>,
- <480000000>, <520000000>,
+ <960000000>, <520000000>,
<375000000>, <288000000>,
- <100000000>, <100000000>;
+ <100000000>, <100000000>,
+ <288000000>, <288000000>,
+ <144000000>;
+ assigned-clock-parents =
+ <&cru SCLK_32K_INTR>,
+ <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
};
grf: syscon@ff770000 {
reg = <0x0 0xff770000 0x0 0x1000>;
};
+ wdt: watchdog@ff800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0xff800000 0x0 0x100>;
+ clocks = <&cru PCLK_WDT>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spdif: spdif@ff880000 {
+ compatible = "rockchip,rk3366-spdif";
+ reg = <0x0 0xff880000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac_bus 3>;
+ dma-names = "tx";
+ clock-names = "hclk", "mclk";
+ clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_bus>;
+ status = "disabled";
+ };
+
i2s_2ch: i2s-2ch@ff890000 {
compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
status = "disabled";
};
+ iep: iep@ff900000 {
+ compatible = "rockchip,iep";
+ iommu_enabled = <1>;
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk_iep", "hclk_iep";
+ version = <2>;
+ status = "disabled";
+ };
+
rga: rga@ff920000 {
compatible = "rockchip,rga2";
dev_mode = <1>;
status = "disabled";
};
+ iep_mmu: iep-mmu {
+ dbgname = "iep";
+ compatible = "rockchip,iep_mmu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ status = "disabled";
+ };
+
+ vpu_mmu: vpu_mmu {
+ dbgname = "vpu";
+ compatible = "rockchip,vpu_mmu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ status = "disabled";
+ };
+
+ vdec_mmu: vdec_mmu {
+ dbgname = "vdec";
+ compatible = "rockchip,vdec_mmu";
+ reg = <0x0 0xff9b0480 0x0 0x40>,
+ <0x0 0xff9b04c0 0x0 0x40>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdec_mmu";
+ status = "disabled";
+ };
+
dsihost0: mipi@ff960000 {
- compatible = "rockchip,rk3368-dsi";
+ compatible = "rockchip,rk3366-dsi";
rockchip,prop = <0>;
reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
status = "disabled";
};
+ vpu: vpu_service@ff9a0000 {
+ compatible = "rockchip,vpu_service";
+ rockchip,grf = <&grf>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff9a0000 0x0 0x800>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec", "irq_enc";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
+ reset-names = "video_h", "video_a";
+ name = "vpu_service";
+ dev_mode = <0>;
+ status = "disabled";
+ };
+
+ rkvdec: rkvdec@ff9b0000 {
+ compatible = "rockchip,rkvdec";
+ rockchip,grf = <&grf>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff9b0000 0x0 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
+ resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
+ reset-names = "video_h", "video_a";
+ dev_mode = <2>;
+ name = "rkvdec";
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3366-pinctrl";
rockchip,grf = <&grf>;
<5 15 RK_FUNC_2 &pcfg_pull_none>,
<5 16 RK_FUNC_2 &pcfg_pull_none>;
};
+
+ i2c2_gpio: i2c2-gpio {
+ rockchip,pins =
+ <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
+ <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
i2c3 {
<5 8 RK_FUNC_1 &pcfg_pull_none>,
<5 9 RK_FUNC_1 &pcfg_pull_none>;
};
+
+ i2c4_gpio: i2c4-gpio {
+ rockchip,pins =
+ <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
+ <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
i2c5 {
};
};
+ spdif {
+ spdif_bus: spdif-bus {
+ rockchip,pins =
+ <5 19 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
spi0 {
spi0_clk: spi0-clk {
rockchip,pins =
};
};
+ scr {
+ scr_clk: scr-clk {
+ rockchip,pins =
+ <5 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ scr_io: scr-io {
+ rockchip,pins =
+ <5 9 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ scr_rst: scr-rst {
+ rockchip,pins =
+ <5 10 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ scr_detect: scr-detect {
+ rockchip,pins =
+ <5 11 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins =
/* mac_rxd2 */
<2 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd3 */
- <2 5 RK_FUNC_1 &pcfg_pull_none>,
+ <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_txd2 */
- <2 4 RK_FUNC_1 &pcfg_pull_none>,
+ <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_rxd1 */
<2 3 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd0 */
<2 2 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
- <2 1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_txd0 */
<2 0 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txclkout */
+ <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_crs */
/* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
/* mac_rxclkin */
/* mac_mdio */
<2 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
- <2 12 RK_FUNC_1 &pcfg_pull_none>,
+ <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_clk */
<2 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxer */
eth_phy {
eth_phy_pwr: eth-phy-pwr {
rockchip,pins =
- <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
+ <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
+
+ gpu: gpu@ffa30000 {
+ compatible = "arm,malit764",
+ "arm,malit76x",
+ "arm,malit7xx",
+ "arm,mali-midgard";
+
+ reg = <0x0 0xffa30000 0 0x10000>;
+
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "GPU", "MMU", "JOB";
+
+ clocks = <&cru ACLK_GPU>;
+ clock-names = "clk_mali";
+ operating-points-v2 = <&gpu_opp_table>;
+ status = "disabled";
+ };
+
+ gpu_opp_table: gpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <96000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <192000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <288000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <1125000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1200000>;
+ };
+ };
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff