arm64: dts: rockchip: amend usb-otg related nodes for rk3368-tb

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3328-evb.dts

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
index 3001fbe95710d1a46a7596b04a34b7d65ceb12ae..004d739543e8e671eabac674bbd4a9516493a827 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -61,6 +61,24 @@
                rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
                status = "okay";
        };
+
+       gmac_clkin: external-gmac-clock {
+               compatible = "fixed-clock";
+               clock-frequency = <125000000>;
+               clock-output-names = "gmac_clkin";
+               #clock-cells = <0>;
+       };
+
+       vcc_phy: vcc-phy-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc_phy";
+               regulator-always-on;
+               regulator-boot-on;
+       };
+};
+
+&cpu0 {
+       cpu-supply = <&vdd_arm>;
 };
 
 &emmc {
@@ -75,11 +93,85 @@
        status = "okay";
 };
 
+&gmac2io {
+       phy-supply = <&vcc_phy>;
+       phy-mode = "rgmii";
+       clock_in_out = "input";
+       snps,reset-gpio = <&gpio1 18 GPIO_ACTIVE_LOW>;
+       snps,reset-active-low;
+       snps,reset-delays-us = <0 10000 50000>;
+       assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+       assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmiim1_pins>;
+       tx_delay = <0x26>;
+       rx_delay = <0x11>;
+       status = "okay";
+};
+
+&io_domains {
+       status = "okay";
+
+       vccio1-supply = <&vcc_io>;
+       vccio2-supply = <&vcc_18emmc>;
+       vccio3-supply = <&vcc_io>;
+       vccio4-supply = <&vdd_18>;
+       vccio5-supply = <&vcc_io>;
+       vccio6-supply = <&vcc_io>;
+       pmuio-supply = <&vcc_io>;
+};
+
+&tsadc {
+       status = "okay";
+};
+
+&u2phy {
+       otg-vbus-gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+
+       u2phy_host: host-port {
+               status = "okay";
+       };
+
+       u2phy_otg: otg-port {
+               status = "okay";
+       };
+};
+
+&u3phy {
+       vbus-drv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&u3phy_utmi {
+       status = "okay";
+};
+
+&u3phy_pipe {
+       status = "okay";
+};
+
 &usb20_otg {
        dr_mode = "peripheral";
        status = "okay";
 };
 
+&usb_host0_ehci {
+       status = "okay";
+};
+
+&usb_host0_ohci {
+       status = "okay";
+};
+
+&usbdrd3 {
+       status = "okay";
+};
+
+&usbdrd_dwc3 {
+       status = "okay";
+};
+
 &i2c1 {
        status = "okay";